Open Access. Powered by Scholars. Published by Universities.®
Articles 1 - 3 of 3
Full-Text Articles in Computer Engineering
Design Of Components For A Generic Microprocessor Architecture, Pradnesh R. Mohare
Design Of Components For A Generic Microprocessor Architecture, Pradnesh R. Mohare
Theses
The objective of this thesis was to develop a generic microprocessor design that can be adapted to many of the existing 16 bit microprocessors. Common features of various microprocessors were used to develop the design of many generic components which can then be used to design the required microprocessors instead of custom-designing each one of them separately. The components were designed using a CISC based micro-programmed design approach as that was more suitable in terms of design and verification time for generic implementation. The generic parts designed include the Register File for temporary data storage, the Effective Address Calculator that …
Design, Implementation, And Evaluation Of A Shared-Memory Parellel Processing System (Smpps), Eric H. Staub
Design, Implementation, And Evaluation Of A Shared-Memory Parellel Processing System (Smpps), Eric H. Staub
Theses
As technology reaches its limits of improvements in microprocessor processing speeds, scientists and engineers have to find viable solutions to meet ever-increasing demands for faster processing speed. One such solution is parallel processing. No longer does one have to wait on sequential operations. A specific task can be split in sub-tasks that can run simultaneously, thus reducing the overall execution time of the task.
The design and implementation of these systems is crucial to the effectiveness of parallel systems. A dual-processor SMPPS was designed and implemented in order to demonstrate how multiple processors are a viable solution to increasing the …
Design Of A Communications Interface For A Very High Performance Computer, Jesse Boyd Zydallis
Design Of A Communications Interface For A Very High Performance Computer, Jesse Boyd Zydallis
Theses
PetaFLOPS computing power is the newest goal of Federal Government agencies, in the increasingly active supercomputer field. To obtain this performance goal by the year 2007, sophisticated parallel processing designs are required. To effectively create network interfaces/routers for interprocessor communications in such computer systems, it requires optimal hardware and software codesigns.
An interface is presented for the NJIT New Millennium Computing Point Design, a system that targets 100 TeraFLOPS performance by the year 2005. The router handles store-and-forward switching and wormhole routing for the system.