Computer Engineering Commons^™

Protecting Return Address Integrity For Risc-V Via Pointer Authentication, Yuhe Zhao

Masters Theses

Embedded systems based on lightweight microprocessors are becoming more prevalent in various applications. However, the security of them remains a significant challenge due to the limited resources and exposure to external threats. Especially, some of these devices store sensitive data and control critical devices, making them high-value targets for attackers. Software security is particularly important because attackers can easily access these devices on the internet and obtain control of them by injecting malware.

Return address (RA) hijacking is a common software attack technique used to compromise control flow integrity (CFI) by manipulating memory, such as return-to-libc attacks. Several methods have …

Sel4 On Risc-V - Developing High Assurance Platforms With Modular Open-Source Architectures, Michael A. Doran Jr

Masters Theses

Virtualization is now becoming an industry standard for modern embedded systems. Modern embedded systems can now support multiple applications on a single hardware platform while meeting power and cost requirements. Virtualization on an embedded system is achieved through the design of the hardware-software interface. Instruction set architecture, ISA, defines the hardware-software interface for an embedded system. At the hardware level the ISA, provides extensions to support virtualization.

In addition to an ISA that supports hypervisor extensions it is equally important to provide a hypervisor completely capable of exploiting the benefits of virtualization for securing modern embedded systems. Currently there does …

Evaluation Of Robust Deep Learning Pipelines Targeting Low Swap Edge Deployment, David Carter Cornett

Masters Theses

The deep learning technique of convolutional neural networks (CNNs) has greatly advanced the state-of-the-art for computer vision tasks such as image classification and object detection. These solutions rely on large systems leveraging wattage-hungry GPUs to provide the computational power to achieve such performance. However, the size, weight and power (SWaP) requirements of these conventional GPU-based deep learning systems are not suitable when a solution requires deployment to so called "Edge" environments such as autonomous vehicles, unmanned aerial vehicles (UAVs) and smart security cameras.

The objective of this work is to benchmark FPGA-based alternatives to conventional GPU systems that have the …

A Secure Architecture For Defense Against Return Address Corruption, Grayson J. Bruner

Masters Theses

The advent of the Internet of Things has brought about a staggering level of inter-connectivity between common devices used every day. Unfortunately, security is not a high priority for developers designing these IoT devices. Often times the trade-off of security comes at too high of a cost in other areas, such as performance or power consumption. This is especially prevalent in resource-constrained devices, which make up a large number of IoT devices. However, a lack of security could lead to a cascade of security breaches rippling through connected devices. One of the most common attacks used by hackers is return …

Compound Effects Of Clock And Voltage Based Power Side-Channel Countermeasures, Jacqueline Lagasse

Masters Theses

The power side-channel attack, which allows an attacker to derive secret information from power traces, continues to be a major vulnerability in many critical systems. Numerous countermeasures have been proposed since its discovery as a serious vulnerability, including both hardware and software implementations. Each countermeasure has its own drawback, with some of the highly effective countermeasures incurring large overhead in area and power. In addition, many countermeasures are quite invasive to the design process, requiring modification of the design and therefore additional validation and testing to ensure its accuracy. Less invasive countermeasures that do not require directly modifying the system …

Oracle Guided Incremental Sat Solving To Reverse Engineer Camouflaged Circuits, Xiangyu Zhang

Masters Theses

This study comprises two tasks. The first is to implement gate-level circuit camouflage techniques. The second is to implement the Oracle-guided incremental de-camouflage algorithm and apply it to the camouflaged designs.

The circuit camouflage algorithms are implemented in Python, and the Oracle- guided incremental de-camouflage algorithm is implemented in C++. During this study, I evaluate the Oracle-guided de-camouflage tool (Solver, in short) performance by de-obfuscating the ISCAS-85 combinational benchmarks, which are camouflaged by the camouflage algorithms. The results show that Solver is able to efficiently de-obfuscate the ISCAS-85 benchmarks regardless of camouflaging style, and is able to do so 10.5x …

Variation Aware Placement For Efficient Key Generation Using Physically Unclonable Functions In Reconfigurable Systems, Shrikant S. Vyas

Masters Theses

With the importance of data security at its peak today, many reconfigurable systems are used to provide security. This protection is often provided by FPGA-based encrypt/decrypt cores secured with secret keys. Physical unclonable functions (PUFs) use random manufacturing variations to generate outputs that can be used in keys. These outputs are specific to a chip and can be used to create device-tied secret keys. Due to reliability issues with PUFs, key generation with PUFs typically requires error correction techniques. This can result in substantial hardware costs. Thus, the total cost of a $n$-bit key far exceeds just the cost of …

Processor Temperature And Reliability Estimation Using Activity Counters, Mayank Chhablani

Masters Theses

With the advent of technology scaling lifetime reliability is an emerging threat in high-performance and deadline-critical systems. High on-chip thermal gradients accelerates localised thermal elevations (hotspots) which increases the aging rate of the semiconductor devices. As a result, reliable operation of the processors has become a challenging task. Therefore, cost effective schemes for estimating temperature and reliability are crucial. In this work we present a reliability estimation scheme that is based on a light-weight temperature estimation technique that monitors hardware events. Unlike previously pro- posed hardware counter-based approaches, our approach involves a linear-temporal-feedback estimator, taking into account the effects of …

Dividing And Conquering Meshes Within The Nist Fire Dynamics Simulator (Fds) On Multicore Computing Systems, Donald Charles Collins

Masters Theses

The National Institute for Standards and Technology (NIST) Fire Dynamics Simulator (FDS) provides a computational fluid dynamics model of a fire, which can be visualized by using NIST Smokeview (SMV). Users must create a configuration file (*.fds) that describes the environment and other characteristics of the fire scene so that the FDS software can produce the output file (*.smv) needed for visualization.The processing can be computationally intensive, often taking between several minutes and several hours to complete. In many cases, a user will create a file that is not optimized for a multicore computing system. By dividing meshes within the …

Function Verification Of Combinational Arithmetic Circuits, Duo Liu

Masters Theses

Hardware design verification is the most challenging part in overall hardware design process. It is because design size and complexity are growing very fast while the requirement for performance is ever higher. Conventional simulation-based verification method cannot keep up with the rapid increase in the design size, since it is impossible to exhaustively test all input vectors of a complex design. An important part of hardware verification is combinational arithmetic circuit verification. It draws a lot of attention because flattening the design into bit-level, known as the bit-blasting problem, hinders the efficiency of many current formal techniques. The goal of …

A Secure Reconfigurable System-On-Programmable-Chip Computer System, William Herbert Collins

Masters Theses

A System-on-Programmable-Chip (SoPC) architecture is designed to meet two goals: to provide a role-based secure computing environment and to allow for user reconfiguration. To accomplish this, a secure root of trust is derived from a fixed architectural subsystem, known as the Security Controller. It additionally provides a dynamically configurable single point of access between applications developed by users and the objects those applications use. The platform provides a model for secrecy such that physical recovery of any one component in isolation does not compromise the system. Dual-factor authentication is used to verify users. A model is also provided for tamper …

An Fpga Based Implementation Of The Exact Stochastic Simulation Algorithm, Phani Bharadwaj Vanguri

Masters Theses

Mathematical and statistical modeling of biological systems is a desired goal for many years. Many biochemical models are often evaluated using a deterministic approach, which uses differential equations to describe the chemical interactions. However, such an approach is inaccurate for small species populations as it neglects the discrete representation of population values, presents the possibility of negative populations, and does not represent the stochastic nature of biochemical systems. The Stochastic Simulation Algorithm (SSA) developed by Gillespie is able to properly account for these inherent noise fluctuations. Due to the stochastic nature of the Monte Carlo simulations, large numbers of simulations …