Computer Engineering Commons^™

Energy And Performance Balancing Architecture For Asynchronous Data Processing Platforms, Chien-Wei Lo

Graduate Theses and Dissertations

The semiconductor industry has been increasingly focused on the energy consumption and heat generation in CMOS-based integrated circuits (ICs) for its dominating impact on the system performance and reliability. Without clock-related timing constraints, asynchronous circuits have demonstrated unique flexibility in performance-energy tradeoffs compared to synchronous designs. This dissertation work presents the architecture capable of balancing energy and performance for asynchronous digital signal processing circuits using the Multi-Threshold NULL Convention Logic (MTNCL). Architecture implementing user-configurable adaptive dynamic voltage scaling (DVS) and data processing core disabling based on the detection and parameterization of system throughput are developed for MTNCL parallel homogeneous and …

Operating System Identification By Ipv6 Communication Using Machine Learning Ensembles, Adrian Ordorica

Graduate Theses and Dissertations

Operating system (OS) identification tools, sometimes called fingerprinting tools, are essential for the reconnaissance phase of penetration testing. While OS identification is traditionally performed by passive or active tools that use fingerprint databases, very little work has focused on using machine learning techniques. Moreover, significantly more work has focused on IPv4 than IPv6. We introduce a collaborative neural network ensemble that uses a unique voting system and a random forest ensemble to deliver accurate predictions. This approach uses IPv6 features as well as packet metadata features for OS identification. Our experiment shows that our approach is valid and we achieve …

A Hybrid Partially Reconfigurable Overlay Supporting Just-In-Time Assembly Of Custom Accelerators On Fpgas, Zeyad Tariq Aklah

Graduate Theses and Dissertations

The state of the art in design and development flows for FPGAs are not sufficiently mature to allow programmers to implement their applications through traditional software development flows. The stipulation of synthesis as well as the requirement of background knowledge on the FPGAs' low-level physical hardware structure are major challenges that prevent programmers from using FPGAs. The reconfigurable computing community is seeking solutions to raise the level of design abstraction at which programmers must operate, and move the synthesis process out of the programmers' path through the use of overlays. A recent approach, Just-In-Time Assembly (JITA), was proposed that enables …

Power Efficient High Temperature Asynchronous Microcontroller Design, Nathan William Kuhns

Graduate Theses and Dissertations

There is an increasing demand for dependable and efficient digital circuitry capable of operating in high temperature environments. Extreme temperatures have adverse effects on traditional silicon synchronous systems because of the changes in delay and setup and hold times caused by the variances in each device’s threshold voltage. This dissertation focuses on the design of the major functionality of an asynchronous 8051 microcontroller in Raytheon’s high temperature Silicon Carbide process, rated for operation over 300ºC. The microcontroller is designed in NULL Convention Logic, for which the traditional bus architecture used for data transfer would consume a large amount of power. …

Exploiting Hardware Abstraction For Parallel Programming Framework: Platform And Multitasking, Hongyuan Ding

Graduate Theses and Dissertations

With the help of the parallelism provided by the fine-grained architecture, hardware accelerators on Field Programmable Gate Arrays (FPGAs) can significantly improve the performance of many applications. However, designers are required to have excellent hardware programming skills and unique optimization techniques to explore the potential of FPGA resources fully. Intermediate frameworks above hardware circuits are proposed to improve either performance or productivity by leveraging parallel programming models beyond the multi-core era.

In this work, we propose the PolyPC (Polymorphic Parallel Computing) framework, which targets enhancing productivity without losing performance. It helps designers develop parallelized applications and implement them on FPGAs. …