Computer Engineering Commons^™

Imprecise Probabilities In Engineering Analyses, Michael Beer, Scott Ferson, Vladik Kreinovich

Departmental Technical Reports (CS)

Probabilistic uncertainty and imprecision in structural parameters and in environmental conditions and loads are challenging phenomena in engineering analyses. They require appropriate mathematical modeling and quantification to obtain realistic results when predicting the behavior and reliability of engineering structures and systems. But the modeling and quantification is complicated by the characteristics of the available information, which involves, for example, sparse data, poor measurements and subjective information. This raises the question whether the available information is sufficient for probabilistic modeling or rather suggests a set-theoretical approach. The framework of imprecise probabilities provides a mathematical basis to deal with these problems which …

An Exploration Of Social Media Use Among Multiply Minoritized Lgbtq Youth, Alfie Leanna Lucero

Open Access Theses & Dissertations

This study responds to a need for research in a fast-growing and significant area of study, that of exploring, understanding, and documenting the numerous ways that multiply marginalized LGBTQ youth between the ages of 14 and 17 use social media. The primary research question examined whether social media provide safe spaces for multiply minoritized LGBTQ youth to express and explore issues of sexuality and gender. In addition, the study explores and categorizes multiple ways that the participants interact with social media and makes comparisons to prior work with more general populations. The study provides descriptions of the participants in terms …

Efficient, Scalable, Parallel, Matrix-Matrix Multiplication, Enrique Portillo

Open Access Theses & Dissertations

For the past decade, power/energy consumption has become a limiting factor for large-scale and embedded High Performance Computing (HPC) systems. This is especially true for systems that include accelerators, e.g., high-end computing devices, such as Graphics Processing Units (GPUs), with terascale computing capabilities and high power draws that greatly surpass that of multi-core CPUs. Accordingly, improving the node-level power/energy efficiency of an application can have a direct and positive impact on both classes of HPC systems.

The research reported in this thesis explores the use of software techniques to enhance the execution-time and power-consumption performance of applications executed on a …

Asynchronous Logic Design With Increased Fault Tolerance And Optimized For Subthreshold Operation, Ivan Santos

Open Access Theses & Dissertations

Synchronization has always been an essential feature in electronic circuits, in which functionality is achieved by an appropriate flow of data with respect to time. An ideal concept of logic design would require every operation to happen instantly; however, the application of this principle to electronics is governed by the laws of physics, which influence the time to execute a process. In fact, the speed at which a microprocessor can perform logic operations is determined by the time that charging and discharging capacitive loads requires, and the time that electric signals spend when traveling through the circuitry. Consequently, the variation …

A Case Study Towards Verification Of The Utility Of Analytical Models In Selecting Checkpoint Intervals, Michael Joseph Harney

Open Access Theses & Dissertations

As high performance computing (HPC) systems grow larger, with increasing numbers of components, failures become more common. Codes that utilize large numbers of nodes and run for long periods of time must take such failures into account and adopt fault tolerance mechanisms to avoid loss of computation and, thus, system utilization. One of those mechanisms is checkpoint/restart. Although analytical models exist to guide users in the selection of an appropriate checkpoint interval, these models are based on assumptions that may not always be true. This thesis examines some of these assumptions, in particular, the consistency of parameters like Mean Time …

Anasic Design And Test Methodology For An Undergraduate Design And Fabrication Project, Arun Joseph Kurian

Open Access Theses & Dissertations

During the 1990's the main focus of chip design methodologies was on the timings and area constraints. Power consumption was considered significant only after a drastic increase of device densities from 130nm on as well as dramatic increases in sub threshold leakage. As technology advanced from 130nm to 90nm and below there was a significant increase in leakage current due to lower threshold voltage and the influence of the deep submicron effects. High power consumption causes different problems such as increasing the cost of the product, reducing the reliability, reducing the battery life among others. Therefore EDA tools were designed …