Computer Engineering Commons^™

Protocol Guided Trace Analysis For Post-Silicon Debug Under Limited Observability, Yuting Cao Cao

USF Tampa Graduate Theses and Dissertations

This thesis considers the problem of reconstructing system level behavior of an SoC design from a partially observed signal trace. Solving this problem is a critical activity in post-silicon validation, and currently depends primarily on human creativity and insights. In this thesis, we provide algorithms to automatically infer system level flows from incomplete, ambiguous, and noisy trace data. This thesis also demonstrates the approach on two case studies, a multicore SoC model developed within the within the GEM5 environment, and a cycle accurate register transfer level model of a similar SoC design.