Computer Engineering Commons^™

Co-Emulation Of Scan-Chain Based Designs Utilizing Sce-Mi Infrastructure, Bill Jason Pidlaoan Tomas

UNLV Theses, Dissertations, Professional Papers, and Capstones

Simulation times of complex System-on-Chips (SoC) have grown exponentially as designs reach the multi-million ASIC gate range. Verification teams have adopted emulation as a prominent methodology, incorporating high-level testbenches and FPGA/ASIC hardware for system-level testing (SLT). In addition to SLT, emulation enables software teams to incorporate software applications with cycle-accurate hardware early on in the design cycle. The Standard for Co-Emulation Modeling Interface (SCE-MI) developed by the Accelera Initiative, is a widely used communication protocol for emulation which has been accepted by major electronic design automation (EDA) companies.

Scan-chain is a design-for-test (DFT) methodology used for testing digital circuits. To …

Significance Of Logic Synthesis In Fpga-Based Design Of Image And Signal Processing Systems, Mariusz Rawski, Henry Selvaraj, Bogdan J. Falkowski, Tadeusz Luba

Electrical & Computer Engineering Faculty Research

This chapter, taking FIR filters as an example, presents the discussion on efficiency of different implementation methodologies of DSP algorithms targeting modern FPGA architectures. Nowadays, programmable technology provides the possibility to implement digital systems with the use of specialized embedded DSP blocks. However, this technology gives the designer the possibility to increase efficiency of designed systems by exploitation of parallelisms of implemented algorithms. Moreover, it is possible to apply special techniques, such as distributed arithmetic (DA). Since in this approach, general-purpose multipliers are replaced by combinational LUT blocks, it is possible to construct digital filters of very high performance. Additionally, …

Implementation Of Large Neural Networks Using Decomposition, Henry Selvaraj, H. Niewiadomski, P. Buciak, M. Pleban, Piotr Sapiecha, Tadeusz Luba, Venkatesan Muthukumar

Electrical & Computer Engineering Faculty Research

The article presents methods of dealing with huge data in the domain of neural networks. The decomposition of neural networks is introduced and its efficiency is proved by the authors’ experiments. The examinations of the effectiveness of argument reduction in the above filed, are presented. Authors indicate, that decomposition is capable of reducing the size and the complexity of the learned data, and thus it makes the learning process faster or, while dealing with large data, possible. According to the authors experiments, in some cases, argument reduction, makes the learning process harder.

A General Approach To Boolean Function Decomposition And Its Application In Fpgabased Synthesis, Tadeusz Luba, Henry Selvaraj

Electrical & Computer Engineering Faculty Research

An effective logic synthesis procedure based on parallel and serial decomposition of a Boolean function is presented in this paper. The decomposition, carried out as the very first step of the .synthesis process, is based on an original representation of the function by a set of r-partitions over the set of minterms. Two different decomposition strategies, namely serial and parallel, are exploited by striking a balance between the two ideas. The presented procedure can be applied to completely or incompletely specified, single- or multiple-output functions and is suitable for different types of FPGAs including XILINX, ACTEL and ALGOTRONIX devices. The …