Open Access. Powered by Scholars. Published by Universities.®
Articles 1 - 3 of 3
Full-Text Articles in Computer Engineering
An Adaptive Modular Redundancy Technique To Self-Regulate Availability, Area, And Energy Consumption In Mission-Critical Applications, Rawad N. Al-Haddad
An Adaptive Modular Redundancy Technique To Self-Regulate Availability, Area, And Energy Consumption In Mission-Critical Applications, Rawad N. Al-Haddad
Electronic Theses and Dissertations
As reconfigurable devices' capacities and the complexity of applications that use them increase, the need for self-reliance of deployed systems becomes increasingly prominent. A Sustainable Modular Adaptive Redundancy Technique (SMART) composed of a dual-layered organic system is proposed, analyzed, implemented, and experimentally evaluated. SMART relies upon a variety of self-regulating properties to control availability, energy consumption, and area used, in dynamically-changing environments that require high degree of adaptation. The hardware layer is implemented on a Xilinx Virtex-4 Field Programmable Gate Array (FPGA) to provide self-repair using a novel approach called a Reconfigurable Adaptive Redundancy System (RARS). The software layer supervises …
Optimizing Dynamic Logic Realizations For Partial Reconfiguration Of Field Programmable Gate Arrays, Matthew Parris
Optimizing Dynamic Logic Realizations For Partial Reconfiguration Of Field Programmable Gate Arrays, Matthew Parris
Electronic Theses and Dissertations
Many digital logic applications can take advantage of the reconfiguration capability of Field Programmable Gate Arrays (FPGAs) to dynamically patch design flaws, recover from faults, or time-multiplex between functions. Partial reconfiguration is the process by which a user modifies one or more modules residing on the FPGA device independently of the others. Partial Reconfiguration reduces the granularity of reconfiguration to be a set of columns or rectangular region of the device. Decreasing the granularity of reconfiguration results in reduced configuration filesizes and, thus, reduced configuration times. When compared to one bitstream of a non-partial reconfiguration implementation, smaller modules resulting in …
Sustainable Fault-Handling Of Reconfigurable Logic Using Throughput-Driven Assessment, Carthik Sharma
Sustainable Fault-Handling Of Reconfigurable Logic Using Throughput-Driven Assessment, Carthik Sharma
Electronic Theses and Dissertations
A sustainable Evolvable Hardware (EH) system is developed for SRAM-based reconfigurable Field Programmable Gate Arrays (FPGAs) using outlier detection and group testing-based assessment principles. The fault diagnosis methods presented herein leverage throughput-driven, relative fitness assessment to maintain resource viability autonomously. Group testing-based techniques are developed for adaptive input-driven fault isolation in FPGAs, without the need for exhaustive testing or coding-based evaluation. The techniques maintain the device operational, and when possible generate validated outputs throughout the repair process. Adaptive fault isolation methods based on discrepancy-enabled pair-wise comparisons are developed. By observing the discrepancy characteristics of multiple Concurrent Error Detection (CED) configurations, …