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Computer Engineering Commons

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Portland State University

2013

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Articles 1 - 7 of 7

Full-Text Articles in Computer Engineering

Trust-But-Verify: Guaranteeing The Integrity Of User-Generated Content In Online Applications, Akshay Dua Sep 2013

Trust-But-Verify: Guaranteeing The Integrity Of User-Generated Content In Online Applications, Akshay Dua

Dissertations and Theses

Online applications that are open to participation lack reliable methods to establish the integrity of user-generated information. Users may unknowingly own compromised devices, or intentionally publish forged information. In these scenarios, applications need some way to determine the "correctness" of autonomously generated information. Towards that end, this thesis presents a "trust-but-verify" approach that enables open online applications to independently verify the information generated by each participant. In addition to enabling independent verification, our framework allows an application to verify less information from more trustworthy users and verify more information from less trustworthy ones. Thus, an application can trade-off performance for …


Self-Timed Dram Data Interface, Rajesh Nerkar Sep 2013

Self-Timed Dram Data Interface, Rajesh Nerkar

Dissertations and Theses

A DRAM communicates with a processing unit via two interfaces: a data interface and a command interface. In today's DRAMs, also known as synchronous DRAMs (SDRAMs), both interfaces use a clock to communicate with the processing unit. The clock times the communication between the processing unit and the SDRAM on both the data interface and the command interface.

We propose a self-timed DRAM. The self-timed DRAM introduces more flexibility into the DRAM interface by eliminating the clock. The command interface and the data interface each communicate with the processing unit using a handshake protocol rather than a clock.

This thesis …


Equivalence Checking For High-Assurance Behavioral Synthesis, Kecheng Hao Jun 2013

Equivalence Checking For High-Assurance Behavioral Synthesis, Kecheng Hao

Dissertations and Theses

The rapidly increasing complexities of hardware designs are forcing design methodologies and tools to move to the Electronic System Level (ESL), a higher abstraction level with better productivity than the state-of-the-art Register Transfer Level (RTL). Behavioral synthesis, which automatically synthesizes ESL behavioral specifications to RTL implementations, plays a central role in this transition. However, since behavioral synthesis is a complex and error-prone translation process, the lack of designers' confidence in its correctness becomes a major barrier to its wide adoption. Therefore, techniques for establishing equivalence between an ESL specification and its synthesized RTL implementation are critical to bring behavioral synthesis …


Designing A Low Cost Prosthetic Arm Device, Samira Rezaei, Frank Fields, Tamara J. Depue May 2013

Designing A Low Cost Prosthetic Arm Device, Samira Rezaei, Frank Fields, Tamara J. Depue

Student Research Symposium

The goal of the project is to build a functional low-cost prosthetic arm that is easily maintained. The focus is on prostheses that attach to the forearm. This design must perform daily life tasks such as picking up, holding and carrying objects while playing and working. To begin the design, a mechanical finger was built with wooden tongue depressors as bone material; rubber bands, string, and drinking straws as muscle material; and masking tape as ligament and tendon material. The length of each joint was set to the golden ratio. Using this method, a basic "hand" was created that could …


A Quantitative Analysis Of Memory Controller Page Policies, Matthew Blackmore Feb 2013

A Quantitative Analysis Of Memory Controller Page Policies, Matthew Blackmore

Dissertations and Theses

Two common goals in computing system design are increasing performance and decreasing power consumption. DRAM-based memory subsystems are a major component of both system performance and power consumption. Memory controllers employ strategies to efficiently schedule DRAM operations to reduce latency and to utilize DRAM low power modes when possible. One of the most important of these is the page policy, which determines when to close pages in DRAM. An effective DRAM memory controller page policy is important to minimizing power consumption and increasing system performance. This thesis explores the impact memory controller page policy has on performance as measured by …


Online Learning In A Chemical Perceptron, Peter Banda, Christof Teuscher, Matthew R. Lakin Jan 2013

Online Learning In A Chemical Perceptron, Peter Banda, Christof Teuscher, Matthew R. Lakin

Computer Science Faculty Publications and Presentations

Autonomous learning implemented purely by means of a synthetic chemical system has not been previously realized. Learning promotes reusability and minimizes the system design to simple input-output specification. In this article we introduce a chemical perceptron, the first full-featured implementation of a perceptron in an artificial (simulated) chemistry. A perceptron is the simplest system capable of learning, inspired by the functioning of a biological neuron. Our artificial chemistry is deterministic and discrete-time, and follows Michaelis-Menten kinetics. We present two models, the weight-loop perceptron and the weight-race perceptron, which represent two possible strategies for a chemical implementation of linear integration and …


Optimal Network Topologies And Resource Mappings For Heterogeneous Networks-On-Chip, Haera Chung Jan 2013

Optimal Network Topologies And Resource Mappings For Heterogeneous Networks-On-Chip, Haera Chung

Dissertations and Theses

Communication has become a bottleneck for modern microprocessors and multi-core chips because metal wires don't scale. The problem becomes worse as the number of components increases and chips become bigger. Traditional Systems-on-Chips (SoCs) interconnect architectures are based on shared-bus communication, which can carry only one communication transaction at a time. This limits the communication bandwidth and scalability. Networks-on-Chip (NoC) were proposed as a promising solution for designing large and complex SoCs. The NoC paradigm provides better scalability and reusability for future SoCs, however, long-distance multi-hop communication through traditional metal wires suffers from both high latency and power consumption. A radical …