Computer Engineering Commons^™

Towards Multipronged On-Chip Memory And Data Protection From Verification To Design And Test, Senwen Kan, Jennifer Dworak

Computer Science and Engineering Theses and Dissertations

Modern System on Chips (SoCs) generally include embedded memories, and these memories may be vulnerable to malicious attacks such as hardware trojan horses (HTHs), test access port exploitation, and malicious software. This dissertation contributes verification as well as design obfuscation solutions aimed at design level detection of memory HTH circuits as well as obfuscation to prevent HTH triggering for embedded memory during functional operation. For malicious attack vectors stemming from test/debug interfaces, this dissertation presents novel solutions that enhance design verification and securitization of an IJTAG based test access interface. Such solutions can enhance SoC protection by preventing memory test …

Enhanced Security Utilizing Side Channel Data Analysis, Michael Taylor

Computer Science and Engineering Theses and Dissertations

The physical state of a system is affected by the activities and processes in which it is tasked with carrying out. In the past there have been many instances where such physical changes have been exploited by bad actors in order to gain insight into the operational state and even the data being held on a system. This method of side channel exploitation is very often effective due to the relative difficulty of obfuscating activity on a physical level. However, in order to take advantage of side channel data streams one must have a detailed working knowledge of how a …

Using A Light-Based Power Source To Defeat Power Analysis Attacks, Remus Valentin Tumac

Computer Science and Engineering Theses and Dissertations

Power analysis attacks exploit the correlation between the information processed by an electronic system and the power consumption of the system. By powering an electronic system with an optical power source, we can prevent meaningful information from being leaked to the power pins and captured in power traces. The relatively constant current draw of the optical power source hides any variability in the power consumption of the target system caused by the logic gates' switching activity of the system as observed at the power pins. This thesis will provide evidence to show that using an optical power source should make …

Reducing Power During Manufacturing Test Using Different Architectures, Yi Sun

Computer Science and Engineering Theses and Dissertations

Power during manufacturing test can be several times higher than power consumption in functional mode. Excessive power during test can cause IR drop, over-heating, and early aging of the chips. In this dissertation, three different architectures have been introduced to reduce test power in general cases as well as in certain scenarios, including field test.

In the first architecture, scan chains are divided into several segments. Every segment needs a control bit to enable capture in a segment when new faults are detectable on that segment for that pattern. Otherwise, the segment should be disabled to reduce capture power. We …