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Full-Text Articles in Computer Engineering
Generic Algorithms And Null Convention Logic Hardware Implementation For Unsigned And Signed Quad-Rail Multiplication, Samarsen Reddy Mallepalli
Generic Algorithms And Null Convention Logic Hardware Implementation For Unsigned And Signed Quad-Rail Multiplication, Samarsen Reddy Mallepalli
Masters Theses
"This thesis focuses on designing generic quad-rail arithmetic circuits, such as signed and unsigned multipliers and Multiply and Accumulate (MAC) units, using the asynchronous delay-insensitive NULL Convention Logic (NCL) paradigm. This work helps to build a library of reusable components to be used for automated NCL circuit synthesis, which will aid in the integration of asynchronous design paradigms into the semiconductor industry"--Abstract, page iii.
Delay-Insensitive Ternary Logic (Ditl), Ravi Sankar Parameswaran Nair
Delay-Insensitive Ternary Logic (Ditl), Ravi Sankar Parameswaran Nair
Masters Theses
"This thesis focuses on development of a Single Rail Ternary Voltage Delay-Insensitive paradigm called Delay-Insensitive Ternary Logic (DITL), which is based on NULL Convention Logic (NCL). Single rail asynchronous logic has potential advantages over Dual-Rail logic such as reduction of Power and Interconnect as well as Logic Area. The DITL concept is developed in steps of individual circuit components. These components are designed at the transistor level and are connected together to form a registered pipeline system. Some variations in pipeline design are also investigated"--Abstract, page iii.