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Full-Text Articles in Computer Engineering
Hardware Implementation Of Image Space Reconstruction Algorithm Using Fpgas, Javier Morales, Nayda Santiago, Miriam Leeser, Alejandro Fernandez
Hardware Implementation Of Image Space Reconstruction Algorithm Using Fpgas, Javier Morales, Nayda Santiago, Miriam Leeser, Alejandro Fernandez
Miriam Leeser
The Image Space Reconstruction Algorithm (ISRA) has been used in hyperspectral imaging applications to monitor changes in the environment and specifically, changes in coral reef, mangrove, and sand in coastal areas. This algorithm is one of a set of iterative methods used in the hyperspectral imaging area to estimate abundance. However, ISRA is highly computational, making it difficult to obtain results in a timely manner. We present the use of specialized hardware in the implementation of this algorithm, specifically the use of VHDL and FPGAs. The implementation of ISRA algorithm has been divided into hardware and software units. The hardware …
Field Programmable Gate Arrays To Accelerate Sub-Surface Imaging Problems, Miriam Leeser
Field Programmable Gate Arrays To Accelerate Sub-Surface Imaging Problems, Miriam Leeser
Miriam Leeser
No abstract provided.
Phase Unwrapping Using Reconfigurable Hardware, Sherman Braganza, Miriam Leeser, W. C. Warger Ii, C. M. Warner, C. A. Dimarzio
Phase Unwrapping Using Reconfigurable Hardware, Sherman Braganza, Miriam Leeser, W. C. Warger Ii, C. M. Warner, C. A. Dimarzio
Miriam Leeser
The most computationally intensive part of the minimum LP Norm phase unwrapping algorithm[1] (its kernel) is the 2D Discrete Cosine Transform(DCT) that computes the variable p in the equation Qp=c using the Preconditioned Conjugate Gradient (PCG) method. The separability of the DCT means that the 2D transform can be decomposed into a series of 1D DCTS that compute the transforms of the rows followed by the transforms of the columns. Furthermore, the DCT can be expressed in terms of a Fast Fourier Transform (FFT), which allows the hardware implementation to use a pre-designed FFT core. This poster presents a design …
Phase Unwrapping Using Reconfigurable Hardware, Sherman Braganza, Miriam Leeser, W. C. Warger Ii, C. M. Warner, C. A. Dimarzio
Phase Unwrapping Using Reconfigurable Hardware, Sherman Braganza, Miriam Leeser, W. C. Warger Ii, C. M. Warner, C. A. Dimarzio
Charles A. DiMarzio
The most computationally intensive part of the minimum LP Norm phase unwrapping algorithm[1] (its kernel) is the 2D Discrete Cosine Transform(DCT) that computes the variable p in the equation Qp=c using the Preconditioned Conjugate Gradient (PCG) method. The separability of the DCT means that the 2D transform can be decomposed into a series of 1D DCTS that compute the transforms of the rows followed by the transforms of the columns. Furthermore, the DCT can be expressed in terms of a Fast Fourier Transform (FFT), which allows the hardware implementation to use a pre-designed FFT core. This poster presents a design …