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Full-Text Articles in Computer Engineering
Evaluating The Use Of Boot Image Encryption On Talos Ii Architecture, Calvin M. Muramoto
Evaluating The Use Of Boot Image Encryption On Talos Ii Architecture, Calvin M. Muramoto
Theses and Dissertations
Sensitive devices operating in unprotected environments are vulnerable to hardware attacks like reverse engineering and side channel analysis. This represents a security concern because the root of trust can be invalidated through boot firmware manipulation. For example, boot data is rarely encrypted and typically travels across an accessible bus like the LPC bus, allowing data to be easily intercepted and possibly manipulated during system startup. The ash chip storing the boot data can also be removed from these devices and examined to reveal detailed boot information. This paper details an implementation of encrypting a section of the boot image and …
Addressing Security Challenges In Embedded Systems And Multi-Tenant Fpgas, Georgios Provelengios
Addressing Security Challenges In Embedded Systems And Multi-Tenant Fpgas, Georgios Provelengios
Doctoral Dissertations
Embedded systems and field-programmable gate arrays (FPGAs) have become crucial parts of the infrastructure that supports our modern technological world. Given the multitude of threats that are present, the need for secure computing systems is undeniably greater than ever. Embedded systems and FPGAs are governed by characteristics that create unique security challenges and vulnerabilities. Despite their array of uses, embedded systems are often built with modest microprocessors that do not support the conventional security solutions used by workstations, such as virus scanners. In the first part of this dissertation, a microprocessor defense mechanism that uses a hardware monitor to protect …
Compound Effects Of Clock And Voltage Based Power Side-Channel Countermeasures, Jacqueline Lagasse
Compound Effects Of Clock And Voltage Based Power Side-Channel Countermeasures, Jacqueline Lagasse
Masters Theses
The power side-channel attack, which allows an attacker to derive secret information from power traces, continues to be a major vulnerability in many critical systems. Numerous countermeasures have been proposed since its discovery as a serious vulnerability, including both hardware and software implementations. Each countermeasure has its own drawback, with some of the highly effective countermeasures incurring large overhead in area and power. In addition, many countermeasures are quite invasive to the design process, requiring modification of the design and therefore additional validation and testing to ensure its accuracy. Less invasive countermeasures that do not require directly modifying the system …
Stealthy Parametric Hardware Trojans In Vlsi Circuits, Samaneh Ghandali
Stealthy Parametric Hardware Trojans In Vlsi Circuits, Samaneh Ghandali
Doctoral Dissertations
Over the last decade, hardware Trojans have gained increasing attention in academia, industry and by government agencies. In order to design reliable countermeasures, it is crucial to understand how hardware Trojans can be built in practice. This is an area that has received relatively scant treatment in the literature. In this thesis, we examine how particularly stealthy parametric Trojans can be introduced to VLSI circuits. Parametric Trojans do not require any additional logic and are purely based on subtle manipulations on the sub-transistor level to modify the parameters of few transistors which makes them very hard to detect. We introduce …
Hardware Trojan Detection Via Golden Reference Library Matching, Lucas Weaver
Hardware Trojan Detection Via Golden Reference Library Matching, Lucas Weaver
Graduate Theses and Dissertations
Due to the proliferation of hardware Trojans in third party Intellectual Property (IP) designs, the issue of hardware security has risen to the forefront of computer engineering. Because of the miniscule size yet devastating effects of hardware Trojans, few detection methods have been presented that adequately address this problem facing the hardware industry. One such method with the ability to detect hardware Trojans is Structural Checking. This methodology analyzes a soft IP at the register-transfer level to discover malicious inclusions. An extension of this methodology is presented that expands the list of signal functionalities, termed assets, in addition to introducing …
Threat Analysis, Countermeaures And Design Strategies For Secure Computation In Nanometer Cmos Regime, Raghavan Kumar
Threat Analysis, Countermeaures And Design Strategies For Secure Computation In Nanometer Cmos Regime, Raghavan Kumar
Doctoral Dissertations
Advancements in CMOS technologies have led to an era of Internet Of Things (IOT), where the devices have the ability to communicate with each other apart from their computational power. As more and more sensitive data is processed by embedded devices, the trend towards lightweight and efficient cryptographic primitives has gained significant momentum. Achieving a perfect security in silicon is extremely difficult, as the traditional cryptographic implementations are vulnerable to various active and passive attacks. There is also a threat in the form of "hardware Trojans" inserted into the supply chain by the untrusted third-party manufacturers for economic incentives. Apart …
Idpal – A Partially-Adiabatic Energy-Efficient Logic Family: Theory And Applications To Secure Computing, Mihail T. Cutitaru
Idpal – A Partially-Adiabatic Energy-Efficient Logic Family: Theory And Applications To Secure Computing, Mihail T. Cutitaru
Electrical & Computer Engineering Theses & Dissertations
Low-power circuits and issues associated with them have gained a significant amount of attention in recent years due to the boom in portable electronic devices. Historically, low-power operation relied heavily on technology scaling and reduced operating voltage, however this trend has been slowing down recently due to the increased power density on chips. This dissertation introduces a new very-low power partially-adiabatic logic family called Input-Decoupled Partially-Adiabatic Logic (IDPAL) with applications in low-power circuits. Experimental results show that IDPAL reduces energy usage by 79% compared to equivalent CMOS implementations and by 25% when compared to the best adiabatic implementation. Experiments ranging …