Computer Engineering Commons^™

A Memory-Centric Customizable Domain-Specific Fpga Overlay For Accelerating Machine Learning Applications, Atiyehsadat Panahi

Graduate Theses and Dissertations

Low latency inferencing is of paramount importance to a wide range of real time and userfacing Machine Learning (ML) applications. Field Programmable Gate Arrays (FPGAs) offer unique advantages in delivering low latency as well as energy efficient accelertors for low latency inferencing. Unfortunately, creating machine learning accelerators in FPGAs is not easy, requiring the use of vendor specific CAD tools and low level digital and hardware microarchitecture design knowledge that the majority of ML researchers do not possess. The continued refinement of High Level Synthesis (HLS) tools can reduce but not eliminate the need for hardware-specific design knowledge. The designs …

Studying The Effects Of Serpentine Soil On Adapted And Non-Adapted Species Using Arduino Technology, Kiana Saniee, Edward Himelblau, Brian Paavo

STAR Program Research Presentations

Abstract: Serpentine soils are formed from ultramafic rocks and are represent an extreme environment for plants. Serpentine soils are unique in that they carry high concentrations of heavy metals, are nutrient deficient, particularly in calcium, and have poor water retention capabilities. Although these soils constitute harsh conditions for plant growth, there are a number of species that are adapted and even endemic to serpentine soil. Water retention by commercial potting mix was compared with serpentine soil. Also, serpentine adapted and non-adapted species were grown in both soil treatments and physiological data were collected. We used the Arduino electronic platform to …

On High-Performance Parallel Fixed-Point Decimal Multiplier Designs, Ming Zhu

UNLV Theses, Dissertations, Professional Papers, and Capstones

High-performance, area-efficient hardware implementation of decimal multiplication is preferred to slow software simulations in a number of key scientific and financial application areas, where errors caused by converting decimal numbers into their approximate binary representations are not acceptable.

Multi-digit parallel decimal multipliers involve two major stages: (i) the partial product generation (PPG) stage, where decimal partial products are determined by selecting the right versions of the pre-computed multiples of the multiplicand, followed by (ii) the partial product accumulation (PPA) stage, where all the partial products are shifted and then added together to obtain the final multiplication product. In this thesis, …