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Full-Text Articles in Computer Engineering
Virtual Memory Management And Virtual Bus Overloading On Multiple Channel Architectures, John N. Armitstead
Virtual Memory Management And Virtual Bus Overloading On Multiple Channel Architectures, John N. Armitstead
Theses and Dissertations
Today's computational environment requires the processing capabilities available only through parallel architectures. The bottleneck that limits the potential of parallel processing is communication between processors, memories, and other hardware devices. A proposed multiple channel architecture (MCA) utilizes tunable semiconductor lasers and fiber optic cables that serve as the communication medium between processor, memory, and I/O nodes. A memory management unit (MMU) was completely described and implemented in a multiprocessor simulator. A permutation-based interleaving (PBI) scheme was utilized to reduce the chance of memory access collisions. Virtual bus utilization, number of collisions, and message traffic patterns were studied under various amounts …
Design Of A Parallel Discrete Event Simulation Coprocessor, Jacob L. Berlin
Design Of A Parallel Discrete Event Simulation Coprocessor, Jacob L. Berlin
Theses and Dissertations
A Parallel Discrete Event Simulation Coprocessor was designed to off- load the synchronization overhead from the processors executing the application. In a multiprocessor architecture, one coprocessor executes the synchronization routines for each host processor. Speedup can be achieved when the host processor executes the application and the coprocessor concurrently executes synchronization routines. The coprocessor uses a programmable microcode control store to guarantee flexibility in the synchronization routines. The coprocessor uses an Extreme Search Associative Memory to support fast Next Event Queue NEQ management. This associative memory uses bit-serial word-parallel search logic to provide 01 insert and retrieval time of events …
Partitioning Structural Vhdl Circuits For Parallel Execution On Hypercubes, Kevin L. Kapp
Partitioning Structural Vhdl Circuits For Parallel Execution On Hypercubes, Kevin L. Kapp
Theses and Dissertations
Distributing simulations among multiple processors is one approach to reducing VHDL simulation time for large VLSI circuit designs. However, parallel simulation introduces the problem of how to partition the logic gates and system behaviors among the available processors in order to obtain maximum speedup. This research investigates deliberate partitioning algorithms that account for the complex inter-dependency structure of the circuit behaviors. Once an initial partition has been obtained, a border annealing algorithm is used to iteratively improve the partition. In addition, methods of measuring the cost of a partition and relating it to the resulting simulation performance are investigated. Structural …
A Decision Criteria To Select An Associative-Memory Organization That Minimizes The Execution Time Of A Mix Of Associative-Search Operations, David W. Banton
A Decision Criteria To Select An Associative-Memory Organization That Minimizes The Execution Time Of A Mix Of Associative-Search Operations, David W. Banton
Theses and Dissertations
The dissertation develops a decision criteria to select an associative-memory organization that minimizes the execution time of a mix of associative-search operations and a decision criteria to estimate the layout dimensions of each organization for a specified memory size. The dissertation reclassifies Feng's associative-search operations into three hardware-influenced categories: bit-position independent (BPI), record-content independent (RCI); bit-position dependent (BPD), RCI; and BPD, record-content dependent (RCD). It develops a relationship between the categories and three associative-memory organizations: the CAM, the bit-serial word-parallel associative memory (BSWPAM) , and the extreme-search associative memory (ESAM). A version of the CAM, three versions of the BSWPAM, …