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Full-Text Articles in Computer Engineering
Design Of A Parallel Discrete Event Simulation Coprocessor, Jacob L. Berlin
Design Of A Parallel Discrete Event Simulation Coprocessor, Jacob L. Berlin
Theses and Dissertations
A Parallel Discrete Event Simulation Coprocessor was designed to off- load the synchronization overhead from the processors executing the application. In a multiprocessor architecture, one coprocessor executes the synchronization routines for each host processor. Speedup can be achieved when the host processor executes the application and the coprocessor concurrently executes synchronization routines. The coprocessor uses a programmable microcode control store to guarantee flexibility in the synchronization routines. The coprocessor uses an Extreme Search Associative Memory to support fast Next Event Queue NEQ management. This associative memory uses bit-serial word-parallel search logic to provide 01 insert and retrieval time of events …
Design Of A Hardware Discrete Event Simulation Coprocessor, David W. Daniel
Design Of A Hardware Discrete Event Simulation Coprocessor, David W. Daniel
Theses and Dissertations
A hardware discrete event simulation (DES) coprocessor was designed to eliminate synchronization overhead as a possible bottleneck. The target architecture is an eight node Intel iPSC/2 Hypercube, but this design has application to future CPU designs that wish to incorporate on-chip architectural features to better support parallel processor synchronization. A structural description of a general-purpose DES hardware coprocessor is given with approximately 90 percent of the components written at the gate level. The remaining components use low-level behavioral descriptions. While the DES coprocessor microcode implements the Chandy-Misra protocol, general-purpose support for a wide-range of protocols was a primary hardware design …