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Articles 1 - 7 of 7
Full-Text Articles in Computer Engineering
Low Cost Dynamic Architecture Adaptation Schemes For Drowsy Cache Management, Nitin Prakash
Low Cost Dynamic Architecture Adaptation Schemes For Drowsy Cache Management, Nitin Prakash
Masters Theses 1911 - February 2014
Energy consumption and speed of execution have long been recognized as conflicting requirements for processor design. In this work, we have developed a low-cost dynamic architecture adaptation scheme to save leakage power in caches. This design uses voltage scaling to implement drowsy caches. The importance of a dynamic scheme for managing drowsy caches, arises from the fact that not only does cache behavior change from one application to the next, but also during different phases of execution within the same application. We discuss various implementations of our scheme that provide a tradeoff between granularity of control and design complexity. …
Design Of An Open-Source Sata Core For Virtex-4 Fpgas, Cory Gorman
Design Of An Open-Source Sata Core For Virtex-4 Fpgas, Cory Gorman
Masters Theses 1911 - February 2014
Many hard drives manufactured today use the Serial ATA (SATA) protocol to communicate with the host machine, typically a PC. SATA is a much faster and much more robust protocol than its predecessor, ATA (also referred to as Parallel ATA or IDE). Many hardware designs, including those using Field-Programmable Gate Arrays (FPGAs), have a need for a long-term storage solution, and a hard drive would be ideal. One such design is the high-speed Data Acquisition System (DAS) created for the NASA Surface Water and Ocean Topography mission. This system utilizes a Xilinx Virtex-4 FPGA. Although the DAS includes a SATA …
Parallel Mesh Adaptation And Graph Analysis Using Graphics Processing Units, Timothy P. Mcguiness
Parallel Mesh Adaptation And Graph Analysis Using Graphics Processing Units, Timothy P. Mcguiness
Masters Theses 1911 - February 2014
In the field of Computational Fluid Dynamics, several types of mesh adaptation strategies are used to enhance a mesh’s quality, thereby improving simulation speed and accuracy. Mesh smoothing (r-refinement) is a simple and effective technique, where nodes are repositioned to increase or decrease local mesh resolution. Mesh partitioning divides a mesh into sections, for use on distributed-memory parallel machines. As a more abstract form of modeling, graph theory can be used to simulate many real-world problems, and has applications in the fields of computer science, sociology, engineering and transportation, to name a few. One of the more important graph analysis …
Leveraging Multi-Radio Communication For Mobile Wireless Sensor Networks, Jeremy J. Gummeson
Leveraging Multi-Radio Communication For Mobile Wireless Sensor Networks, Jeremy J. Gummeson
Masters Theses 1911 - February 2014
An important challenge in mobile sensor networks is to enable energy-efficient communication over a diversity of distances while being robust to wireless effects caused by node mobility. In this thesis, we argue that the pairing of two complementary radios with heterogeneous range characteristics enables greater range and interference diversity at lower energy cost than a single radio. We make three contributions towards the design of such multi-radio mobile sensor systems. First, we present the design of a novel reinforcement learning-based link layer algorithm that continually learns channel characteristics and dynamically decides when to switch between radios. Second, we describe a …
Post Silicon Clock Tuning System To Mitigate The Impact Of Process Variation On Performance, Kelageri Nagaraj
Post Silicon Clock Tuning System To Mitigate The Impact Of Process Variation On Performance, Kelageri Nagaraj
Masters Theses 1911 - February 2014
Optical shrink for process migration, manufacturing process variation and dynamic voltage control leads to clock skew as well as path delay variation in a manufactured chip. Since such variations are difficult to predict in pre-silicon phase, tunable clock buffers have been used in several microprocessor designs. The buffer delays are tuned to improve maximum operating clock frequency of a design. This however shifts the burden of finding tuning settings for individual clock buffers to the test process. In this project, we describe a process of using tester measurements to determine the settings of the tunable buffers for recovery of performance …
Application Specific Customization And Scalability Of Soft Multiprocessors, Deepak C. Unnikrishnan
Application Specific Customization And Scalability Of Soft Multiprocessors, Deepak C. Unnikrishnan
Masters Theses 1911 - February 2014
Soft multiprocessor systems exploit the plentiful computational resources available in field programmable devices. By virtue of their adaptability and ability to support coarse grained parallelism, they serve as excellent platforms for rapid prototyping and design space exploration of embedded multiprocessor applications. As complex applications emerge, careful mapping, processor and interconnect customization are critical to the overall performance of the multiprocessor system. In this thesis, we have developed an automated scalable framework to efficiently map applications written in a high-level programmer-friendly language to customizable soft-cores. The framework allows the user to specify the application in a high-level language called Streamit. After …
A Hardware Framework For Yield And Reliability Enhancement In Chip Multiprocessors, Abhisek Pan
A Hardware Framework For Yield And Reliability Enhancement In Chip Multiprocessors, Abhisek Pan
Masters Theses 1911 - February 2014
Device reliability and manufacturability have emerged as dominant concerns in end-of-road CMOS devices. Today an increasing number of hardware failures are attributed to device reliability problems that cause partial system failure or shutdown. Also maintaining an acceptable manufacturing yield is seen as challenge because of smaller feature sizes, process variation, and reduced headroom for burn-in tests. In this project we investigate a hardware-based scheme for improving yield and reliability of a homogeneous chip multiprocessor (CMP). The proposed solution involves a hardware framework that enables us to utilize the redundancies inherent in a multi-core system to keep the system operational in …