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Articles 1 - 30 of 31
Full-Text Articles in Computer Engineering
Implementation And Characterization Of Ahr On A Xilinx Fpga, Andrew J. Dittrich
Implementation And Characterization Of Ahr On A Xilinx Fpga, Andrew J. Dittrich
Theses and Dissertations
A new version of the Adaptive-Hybrid Redundancy (AHR) architecture was developed to be implemented and tested in hardware using Commercial-Off-The-Shelf (COTS) Field-Programmable Gate Arrays (FPGAs). The AHR architecture was developed to mitigate the effects that the Single Event Upset (SEU) and Single Event Transient (SET) radiation effects have on processors and was tested on a Microprocessor without Interlocked Pipeline Stages (MIPS) architecture. The AHR MIPS architecture was implemented in hardware using two Xilinx FPGAs. A Universal Asynchronous Receiver Transmitter (UART) based serial communication network was added to the AHR MIPS design to enable inter-board communication between the two FPGAs. The …
Evaluating The Use Of Boot Image Encryption On Talos Ii Architecture, Calvin M. Muramoto
Evaluating The Use Of Boot Image Encryption On Talos Ii Architecture, Calvin M. Muramoto
Theses and Dissertations
Sensitive devices operating in unprotected environments are vulnerable to hardware attacks like reverse engineering and side channel analysis. This represents a security concern because the root of trust can be invalidated through boot firmware manipulation. For example, boot data is rarely encrypted and typically travels across an accessible bus like the LPC bus, allowing data to be easily intercepted and possibly manipulated during system startup. The ash chip storing the boot data can also be removed from these devices and examined to reveal detailed boot information. This paper details an implementation of encrypting a section of the boot image and …
Securing Infiniband Networks With End-Point Encryption, Noah B. Diamond
Securing Infiniband Networks With End-Point Encryption, Noah B. Diamond
Theses and Dissertations
The NVIDIA-Mellanox Bluefield-2 is a 100 Gbps high-performance network interface which offers hardware offload and acceleration features that can operate directly on network traffic without routine involvement from the ARM CPU. This allows the ARM multi-core CPU to orchestrate the hardware to perform operations on both Ethernet and RDMA traffic at high rates rather than processing all the traffic directly. A testbed called TNAP was created for performance testing and a MiTM verification process called MiTMVMP is used to ensure proper network configuration. The hardware accelerators of the Bluefield-2 support a throughput of nearly 86 Gbps when using IPsec to …
Design, Development, And Testing Of Embedded Computing On Afit's Control & Autonomy Space Proximity Robot (Caspr), Collin A. Gwaltney
Design, Development, And Testing Of Embedded Computing On Afit's Control & Autonomy Space Proximity Robot (Caspr), Collin A. Gwaltney
Theses and Dissertations
This thesis reviews RPO algorithm testbeds and discusses the development of the Control and Autonomy Space proximity Robot (CASpR) kinematic testbed housed at the Air Force Institute of Technology (AFIT). CASpR operates on a rail system to propagate the trajectories of two satellites using the Hill-Clohessy-Wiltshire (HCW) Equations of Motion (EOMs). In this study, the implementation of a Jetson TX2i as an onboard flight computer is discussed and accomplished. Each hardware component used in the process of adding embedded computing as well as the software and paths of communication are all discussed in detail. Tests are conducted to assess the …
Physically Unclonable Characteristics For Verification Of Transmon-Based Quantum Computers, Leleia A. Hsia
Physically Unclonable Characteristics For Verification Of Transmon-Based Quantum Computers, Leleia A. Hsia
Theses and Dissertations
Future national security can be strengthened by verifying and securing the quantum computing supply chain. This dissertation proposes physically unclonable characteristics (PUCs), a method of quantum hardware verification inspired by classical physically unclonable functions, for future application to quantum processors implemented with transmon qubits. Qualitative and quantitative analysis is provided on the development of PUCs, including identifying qubit characteristics and qubit discrimination methods suitable for PUCs. Characteristics tested on IBM Quantum services include T1 and T2 coherence times, single-qubit and multi-qubit gate error rates, readout error rates, quantum process tomography metrics, and random benchmarking metrics. Results show that non-parametric qubit …
Adaptive-Hybrid Redundancy For Radiation Hardening, Nicolas S. Hamilton
Adaptive-Hybrid Redundancy For Radiation Hardening, Nicolas S. Hamilton
Theses and Dissertations
An Adaptive-Hybrid Redundancy (AHR) mitigation strategy is proposed to mitigate the effects of Single Event Upset (SEU) and Single Event Transient (SET) radiation effects. AHR is adaptive because it switches between Triple Modular Redundancy (TMR) and Temporal Software Redundancy (TSR). AHR is hybrid because it uses hardware and software redundancy. AHR is demonstrated to run faster than TSR and use less energy than TMR. Furthermore, AHR allows space vehicle designers, mission planners, and operators the flexibility to determine how much time is spent in TMR and TSR. TMR mode provides faster processing at the expense of greater energy usage. TSR …
Instantaneous Bandwidth Expansion Using Software Defined Radios, Nicholas D. Everett
Instantaneous Bandwidth Expansion Using Software Defined Radios, Nicholas D. Everett
Theses and Dissertations
The Stimulated Unintended Radiated Emissions (SURE) process has been proven capable of classifying a device (e.g. a loaded antenna) as either operational or defective. Currently, the SURE process utilizes a specialized noise radar which is bulky, expensive and not easily supported. With current technology advancements, Software Defined Radios (SDRs) have become more compact, more readily available and significantly cheaper. The research here examines whether multiple SDRs can be integrated to replace the current specialized ultra-wideband noise radar used with the SURE process. The research specifically targets whether or not multiple SDR sub-band collections can be combined to form a wider …
Graph-Based Temporal Analysis In Digital Forensics, Nikolai A. Adderley
Graph-Based Temporal Analysis In Digital Forensics, Nikolai A. Adderley
Theses and Dissertations
Establishing a timeline as part of a digital forensics investigation is a vital part of understanding the order in which system events occurred. However, most digital forensics tools present timelines as histogram or as raw artifacts. Consequently, digital forensics examiners are forced to rely on manual, labor-intensive practices to reconstruct system events. Current digital forensics analysis tools are at their technological limit with the increasing storage and complexity of data. A graph-based timeline can present digital forensics evidence in a structure that can be immediately understood and effortlessly focused. This paper presents the Temporal Analysis Integration Management Application (TAIMA) to …
A Framework For Understanding, Prioritizing, And Applying Systems Security Engineering Processes, Activities, And Tasks, Stephen Khou
A Framework For Understanding, Prioritizing, And Applying Systems Security Engineering Processes, Activities, And Tasks, Stephen Khou
Theses and Dissertations
Current systems security practices lack an effective approach to prioritize and tailor systems security efforts to develop and field secure systems in challenging operational environments, which results in business and mission stakeholders becoming more susceptible to an array of disruptive events. This work informs Systems Engineers on recent developments in the field of system security engineering and provides a framework for more fully understanding the application of Systems Security Engineering (SSE) processes, activities, and tasks as described in the recently released National Institute of Standards and Technology (NIST) Special Publication 800-160. This SSE framework uniquely offers a repeatable and tailorable …
An Analysis Of Conus Based Deployment Of Pseudolites For Positioning, Navigation And Timing (Pnt) Systems, Justin H. Deifel, Albert J. Pena
An Analysis Of Conus Based Deployment Of Pseudolites For Positioning, Navigation And Timing (Pnt) Systems, Justin H. Deifel, Albert J. Pena
Theses and Dissertations
The Global Positioning System (GPS) developed and operated by the United States Air Force (USAF) provides a way for users to determine position, navigation and timing (PNT). GPS provides an extraordinary capability that has become instrumental in all aspects of our day to day lives. As new technologies such as automated vehicles and unmanned aircraft continue to be developed, a reliable back up to GPS is required to ensure the PNT data generated in these systems is accurate. This research studies a potential architecture for deploying a nationwide network of ground based pseudolites that would act to supplement and backup …
Situational Awareness/Triage Tool For Use In A Chemical, Biological, Radiological Nuclear Explosive (Cbrne) Environment, John N. Scarlett, Heather L. Gallup, David A. Smith
Situational Awareness/Triage Tool For Use In A Chemical, Biological, Radiological Nuclear Explosive (Cbrne) Environment, John N. Scarlett, Heather L. Gallup, David A. Smith
AFIT Patents
A method of managing patient care and emergency response following a Chemical, Biological, Radiological, or Nuclear Explosive (CBRNE) attack and maintaining compliance with the Health Insurance Portability and Accountability Act (HIPAA). The method including identifying each patient with a unique patient identifier, the identifier based upon the geospatial location of the patient, the geospatial location including at least the latitude and longitude of the patient when first treated, the unique patient identifier being part of patient data. Providing a collection point of patient data to form a patient data database where in the patient location data may be used to …
Radio Frequency Based Programmable Logic Controller Anomaly Detection, Samuel J. Stone
Radio Frequency Based Programmable Logic Controller Anomaly Detection, Samuel J. Stone
Theses and Dissertations
The research goal involved developing improved methods for securing Programmable Logic Controller (PLC) devices against unauthorized entry and mitigating the risk of Supervisory Control and Data Acquisition (SCADA) attack by detecting malicious software and/or trojan hardware. A Correlation Based Anomaly Detection (CBAD) process was developed to enable 1) software anomaly detection discriminating between various operating conditions to detect malfunctioning or malicious software, firmware, etc., and 2) hardware component discrimination discriminating between various hardware components to detect malfunctioning or counterfeit, trojan, etc., components.
File Carving And Malware Identification Algorithms Applied To Firmware Reverse Engineering, Karl A . Sickendick
File Carving And Malware Identification Algorithms Applied To Firmware Reverse Engineering, Karl A . Sickendick
Theses and Dissertations
Modern society depends on critical infrastructure (CI) managed by Programmable Logic Controllers (PLCs). PLCs depend on firmware, though firmware security vulnerabilities and contents remain largely unexplored. Attackers are acquiring the knowledge required to construct and install malicious firmware on CI. To the defender, firmware reverse engineering is a critical, but tedious, process. This thesis applies machine learning algorithms, from the le carving and malware identification fields, to firmware reverse engineering. It characterizes the algorithms' performance. This research describes and characterizes a process to speed and simplify PLC firmware analysis. The system partitions binary firmwares into segments, labels each segment with …
External Verification Of Scada System Embedded Controller Firmware, Lucille R. Mcminn
External Verification Of Scada System Embedded Controller Firmware, Lucille R. Mcminn
Theses and Dissertations
Critical infrastructures such as oil and gas pipelines, the electric power grid, and railways, rely on the proper operation of supervisory control and data acquisition (SCADA) systems. Current SCADA systems, however, do not have sufficient tailored electronic security solutions. Solutions available are developed primarily for information technology (IT) systems. Indeed, the toolkit for SCADA incident prevention and response is unavailing as the operating parameters associated with SCADA systems are different from IT systems. The unique environment necessitates tailored solutions. Consider the programmable logic controllers (PLCs) that directly connect to end physical systems for control and monitoring of operating parameters -- …
Extracting Forensic Artifacts From Windows O/S Memory, James S. Okolica, Gilbert L. Peterson
Extracting Forensic Artifacts From Windows O/S Memory, James S. Okolica, Gilbert L. Peterson
AFIT Documents
Memory analysis is a rapidly growing area in both digital forensics and cyber situational awareness (SA). Memory provides the most accurate snapshot of what is occurring on a computer at a moment in time. By combining it with event and network logs as well as the files present on the filesystem, an analyst can re-create much of what has occurred and is occuring on a computer. The Compiled Memory Analysis Tool (CMAT) takes either a disk image of memory from a Windows operating system or an interface into a virtual machine running a Windows operating system and extracts forensic artifacts …
Automated Analysis Of Arm Binaries Using The Low-Level Virtual Machine Compiler Framework, Jeffrey B. Scott
Automated Analysis Of Arm Binaries Using The Low-Level Virtual Machine Compiler Framework, Jeffrey B. Scott
Theses and Dissertations
Binary program analysis is a critical capability for offensive and defensive operations in Cyberspace. However, many current techniques are ineffective or time-consuming and few tools can analyze code compiled for embedded processors such as those used in network interface cards, control systems and mobile phones. This research designs and implements a binary analysis system, called the Architecture-independent Binary Abstracting Code Analysis System (ABACAS), which reverses the normal program compilation process, lifting binary machine code to the Low-Level Virtual Machine (LLVM) compiler's intermediate representation, thereby enabling existing security-related analyses to be applied to binary programs. The prototype targets ARM binaries but …
Dynamic Polymorphic Reconfiguration To Effectively “Cloak” A Circuit’S Function, Jeffrey L. Falkinburg
Dynamic Polymorphic Reconfiguration To Effectively “Cloak” A Circuit’S Function, Jeffrey L. Falkinburg
Theses and Dissertations
Today's society has become more dependent on the integrity and protection of digital information used in daily transactions resulting in an ever increasing need for information security. Additionally, the need for faster and more secure cryptographic algorithms to provide this information security has become paramount. Hardware implementations of cryptographic algorithms provide the necessary increase in throughput, but at a cost of leaking critical information. Side Channel Analysis (SCA) attacks allow an attacker to exploit the regular and predictable power signatures leaked by cryptographic functions used in algorithms such as RSA. In this research the focus on a means to counteract …
Image Processing For Multiple-Target Tracking On A Graphics Processing Unit, Michael A. Tanner
Image Processing For Multiple-Target Tracking On A Graphics Processing Unit, Michael A. Tanner
Theses and Dissertations
Multiple-target tracking (MTT) systems have been implemented on many different platforms, however these solutions are often expensive and have long development times. Such MTT implementations require custom hardware, yet offer very little flexibility with ever changing data sets and target tracking requirements. This research explores how to supplement and enhance MTT performance with an existing graphics processing unit (GPU) on a general computing platform. Typical computers are already equipped with powerful GPUs to support various games and multimedia applications. However, such GPUs are not currently being used in desktop MTT applications. This research explores if and how a GPU can …
Optimal Guidance Of A Relay Mav For Isr Support Beyond Line-Of-Sight, John H. Hansen
Optimal Guidance Of A Relay Mav For Isr Support Beyond Line-Of-Sight, John H. Hansen
Theses and Dissertations
This thesis developed guidance laws to optimally position a relay Micro-UAV (MAV) to provide an operator with real-time Intelligence, Surveillance, and Reconnaissance (ISR) by relaying communication and video signals when there is no line-of-sight between the operator at the base and the rover MAV performing the ISR mission. The ISR system consists of two MAVs, the Relay and the Rover, and a Base. The Relay strives to position itself to minimize the radio frequency (RF) power required for maintaining communications between the Rover and the Base, while the Rover performs the ISR mission, which may maximize the required RF power. …
Hardware Algorithm Implementation For Mission Specific Processing, Jason W. Shirley
Hardware Algorithm Implementation For Mission Specific Processing, Jason W. Shirley
Theses and Dissertations
There is a need to expedite the process of designing military hardware to stay ahead of the adversary. The core of this project was to build reusable, synthesizeable libraries to make this a possibility. In order to build these libraries, Matlab® commands and functions, such as Conv2, Round, Floor, Pinv, etc., had to be converted into reusable VHDL modules. These modules make up reusable libraries for the Mission Specific Process (MSP) which will support AFRL/RY. The MSP allows the VLSI design process to be completed in a mere matter of days or months using an FPGA or ASIC design, as …
Radar System Characterization Extended To Hardware In The Loop Simulation For The Lab-Volt™ Training System, Oscar C. Mayhew
Radar System Characterization Extended To Hardware In The Loop Simulation For The Lab-Volt™ Training System, Oscar C. Mayhew
Theses and Dissertations
Modeling RADAR signals in software allows the testing of potential electronic counter measures and electronic counter counter measures without the associated RADAR hardware and test facilities. Performing a characterization process on a real world RADAR system reveals all imperfections within the system. The Lab-Volt™ RADAR system served as the characterized real world RADAR system. The characterization process consisted of measurements at selected front panel locations on the Lab-Volt™ transmitter module, antenna pedestal, receiver module, and dual channel sampler module. Due to the overwhelming influence of antenna parameters on a received signal, the characterization process also attempted to derive an antenna …
Real-Time Gps-Alternative Navigation Using Commodity Hardware, Jordon L. Fletcher
Real-Time Gps-Alternative Navigation Using Commodity Hardware, Jordon L. Fletcher
Theses and Dissertations
Modern navigation systems can use the Global Positioning System (GPS) to accurately determine position with precision in some cases bordering on millimeters. Unfortunately, GPS technology is susceptible to jamming, interception, and unavailability indoors or underground. There are several navigation techniques that can be used to navigate during times of GPS unavailability, but there are very few that result in GPS-level precision. One method of achieving high precision navigation without GPS is to fuse data obtained from multiple sensors. This thesis explores the fusion of imaging and inertial sensors and implements them in a real-time system that mimics human navigation. In …
Aphid: Anomaly Processor In Hardware For Intrusion Detection, Samuel A. Hart
Aphid: Anomaly Processor In Hardware For Intrusion Detection, Samuel A. Hart
Theses and Dissertations
The Anomaly Processor in Hardware for Intrusion Detection (APHID) is a step forward in the field of co-processing intrusion detection mechanism. By using small, fast hardware primitives APHID relieves the production CPU from the burden of security processing. These primitives are tightly coupled to the CPU giving them access to critical state information such as the current instruction(s) in execution, the next instruction, registers, and processor state information. By monitoring these hardware elements, APHID is able to determine when an anomalous action occurs within one clock cycle. Upon detection, APHID can force the processor into a corrective state, or a …
Hardware Virtualization Applied To Rootkit Defense, Douglas P. Medley
Hardware Virtualization Applied To Rootkit Defense, Douglas P. Medley
Theses and Dissertations
This research effort examines the idea of applying virtualization hardware to enhance operating system security against rootkits. Rootkits are sets of tools used to hide code and/or functionality from the user and operating system. Rootkits can accomplish this feat through using access to one part of an operating system to change another part that resides at the same privilege level. Hardware assisted virtualization (HAV) provides an opportunity to defeat this tactic through the introduction of a new operating mode. Created to aid operating system virtualization, HAV provides hardware support for managing and saving multiple states of the processor. This hardware …
Hardware Realization Of A Transform Domain Communication System, Marshall E. Haker
Hardware Realization Of A Transform Domain Communication System, Marshall E. Haker
Theses and Dissertations
The purpose of this research was to implement a Transform Domain Communication System (TDCS) in hardware and compare experimental bit error performance with results published in literature. The intent is to demonstrate the effectiveness or ineffectiveness of a TDCS in communicating binary data across a real channel. In this case, an acoustic channel that is laden with narrowband interference was considered. A TDCS user pair was constructed to validate the proposed design using Matlab™ to control a PC sound card. The proposed TDCS design used the Bartlett method of spectrum estimation, the spectral notching algorithm found in TDCS literature, quadrature …
Congruent Weak Conformance, Ronald W. Brower
Congruent Weak Conformance, Ronald W. Brower
Theses and Dissertations
This research addresses the problem of verifying implementations against specifications through an innovative logic approach. Congruent weak conformance, a formal relationship between agents and specifications, has been developed and proven to be a congruent partial order. This property arises from a set of relations called weak conformations. The largest, called weak conformance, is analogous to Milner's observational equivalence. Weak conformance is not an equivalence, however, but rather an ordering relation among processes. Weak conformance allows behaviors in the implementation that are unreachable in the specification. Furthermore, it exploits output concurrencies and allows interleaving of extraneous output actions in the implementation. …
Rapid And Accurate Timing Simulation Of Radiation-Hardened Digital Microelectronics Using Vhdl, Charles P. Brothers Jr.
Rapid And Accurate Timing Simulation Of Radiation-Hardened Digital Microelectronics Using Vhdl, Charles P. Brothers Jr.
Theses and Dissertations
This dissertation presents the development of a fast, accurate, timing simulation capability based on VHSIC Hardware Description Language VHDL without the use of back annotation of timing delay information. This VHDL-based timing simulator is intended for use with radiation-hardened microelectronics in simulating timing of circuit operation in pre-radiation, post-radiation 1 MradSi total dose, and ionizing dose radiation environments. Development of the timing models are presented. The implementation of the timing models are incorporated into a VHDL library composed of basic logic gates and flip-flops. Simulations of complex circuits were run in SPICE and VHDL to assess the timing accuracy and …
Virtual Memory Management And Virtual Bus Overloading On Multiple Channel Architectures, John N. Armitstead
Virtual Memory Management And Virtual Bus Overloading On Multiple Channel Architectures, John N. Armitstead
Theses and Dissertations
Today's computational environment requires the processing capabilities available only through parallel architectures. The bottleneck that limits the potential of parallel processing is communication between processors, memories, and other hardware devices. A proposed multiple channel architecture (MCA) utilizes tunable semiconductor lasers and fiber optic cables that serve as the communication medium between processor, memory, and I/O nodes. A memory management unit (MMU) was completely described and implemented in a multiprocessor simulator. A permutation-based interleaving (PBI) scheme was utilized to reduce the chance of memory access collisions. Virtual bus utilization, number of collisions, and message traffic patterns were studied under various amounts …
Design Of A Parallel Discrete Event Simulation Coprocessor, Jacob L. Berlin
Design Of A Parallel Discrete Event Simulation Coprocessor, Jacob L. Berlin
Theses and Dissertations
A Parallel Discrete Event Simulation Coprocessor was designed to off- load the synchronization overhead from the processors executing the application. In a multiprocessor architecture, one coprocessor executes the synchronization routines for each host processor. Speedup can be achieved when the host processor executes the application and the coprocessor concurrently executes synchronization routines. The coprocessor uses a programmable microcode control store to guarantee flexibility in the synchronization routines. The coprocessor uses an Extreme Search Associative Memory to support fast Next Event Queue NEQ management. This associative memory uses bit-serial word-parallel search logic to provide 01 insert and retrieval time of events …
Partitioning Structural Vhdl Circuits For Parallel Execution On Hypercubes, Kevin L. Kapp
Partitioning Structural Vhdl Circuits For Parallel Execution On Hypercubes, Kevin L. Kapp
Theses and Dissertations
Distributing simulations among multiple processors is one approach to reducing VHDL simulation time for large VLSI circuit designs. However, parallel simulation introduces the problem of how to partition the logic gates and system behaviors among the available processors in order to obtain maximum speedup. This research investigates deliberate partitioning algorithms that account for the complex inter-dependency structure of the circuit behaviors. Once an initial partition has been obtained, a border annealing algorithm is used to iteratively improve the partition. In addition, methods of measuring the cost of a partition and relating it to the resulting simulation performance are investigated. Structural …