Computer Engineering Commons^™

Understanding Quadrature Modulation By Designing A 7mhz Iq Test Bench To Encode The Polybius Square, William Lee Bradley

Dissertations and Theses

This thesis outlines the design of an IQ Test Bench that allows for experimentation of quadrature modulation techniques. Quadrature modulation utilizes two signals I and Q, 90° out of phase from each other, to greatly increase communication data rates. Using Desmos, a thorough mathematical analysis of waveform mixing is presented, and constellation diagrams are plotted from the results. From this an ancient fire signaling technique known as the Polybius Square is encoded into the system. The IQ Test Bench is built from fundamental components that would be contained within an RFFE: a local oscillator and two frequency mixers. The LO …

A Privacy-Preserving Strategy For The Trust Layer Of The Energy Grid Of Things Distributed Energy Resource Management System, Mohammed Abdullah Alsaid

Dissertations and Theses

Emergent from the shadows of the traditional grid flaws, the Smart Grid (SG) idea was born and led by government mandates toward cleaner energy production. The SG represents the next generation of electricity distribution systems that subsume recent technological innovations. It uses digital communication between its components and entities to attain more automation, self-sufficiency, and reliability. Unfortunately, this relatively new concept is not flawless; the intrinsic reliance on increased digital communication spreads open attack paths for adversaries. Therefore, finding solutions that address information exchange vulnerabilities has become imperative.

The Energy Grid of Things (EGoT) is Portland State University's implementation of …

Audio Beat Detection With Application To Robot Drumming, Michael James Engstrom

Dissertations and Theses

This Drumming Robot thesis demonstrates the design of a robot which can play drums in rhythm to an external audio source. The audio source can be either a pre-recorded .wav file or a live sample .wav file from a microphone. The dominant beats-per-minute (BPM) of the audio would be extracted and the robot would drum in time to the BPM. A Fourier Analysis-based BPM detection algorithm, developed by Eric Scheirer (Tempo and beat analysis of acoustical musical signals)ⁱ was adopted and implemented. In contrast to other popular algorithms, the main advantage of Scheirer's algorithm is it has …

Silicon Compilation And Test For Dataflow Implementations In Gasp And Click, Swetha Mettala Gilla

Dissertations and Theses

Many modern computer systems are distributed over space. Well-known examples are the Internet of Things and IBM's TrueNorth for deep learning applications. At the Asynchronous Research Center (ARC) at Portland State University we build distributed hardware systems using self-timed computation and delay-insensitive communication. Where appropriate, self-timed hardware operations can reduce average and peak power, energy, latency, and electromagnetic interference. Alternatively, self-timed operations can increase throughput, tolerance to delay variations, scalability, and manufacturability.

The design of complex hardware systems requires design automation and support for test, debug, and product characterization.

This thesis focuses on design compilation and test support for dataflow …

Formal Modeling And Verification Of Delay-Insensitive Circuits, Hoon Park

Dissertations and Theses

Einstein's relativity theory tells us that the notion of simultaneity can only be approximated for events distributed over space. As a result, the use of asynchronous techniques is unavoidable in systems larger than a certain physical size. Traditional design techniques that use global clocks face this barrier of scale already within the space of a modern microprocessor chip. The most common response by the chip industry for overcoming this barrier is to use Globally Asynchronous Locally Synchronous (GALS) design techniques. The circuits investigated in this thesis can be viewed as examples of GALS design. To make such designs trustworthy it …

Detection Of Variable Retention Time In Dram, Neraj Kumar

Dissertations and Theses

This thesis investigates a test method to detect the presence of Variable Retention Time (VRT) bits in manufactured DRAM. The VRT bits retention time is modeled as a 2-state random telegraph process that includes miscorrelation between test and use. The VRT defect is particularly sensitive to test and use conditions. A new test method is proposed to screen the VRT bits by simulating the use conditions during manufacturing test. Evaluation of the proposed test method required a bit-level VRT model to be parameterized as a function of temperature and voltage conditions. The complete 2-state VRT bit model combines models for …

Self-Timed Dram Data Interface, Rajesh Nerkar

Dissertations and Theses

A DRAM communicates with a processing unit via two interfaces: a data interface and a command interface. In today's DRAMs, also known as synchronous DRAMs (SDRAMs), both interfaces use a clock to communicate with the processing unit. The clock times the communication between the processing unit and the SDRAM on both the data interface and the command interface.

We propose a self-timed DRAM. The self-timed DRAM introduces more flexibility into the DRAM interface by eliminating the clock. The command interface and the data interface each communicate with the processing unit using a handshake protocol rather than a clock.

This thesis …

A Quantitative Analysis Of Memory Controller Page Policies, Matthew Blackmore

Dissertations and Theses

Two common goals in computing system design are increasing performance and decreasing power consumption. DRAM-based memory subsystems are a major component of both system performance and power consumption. Memory controllers employ strategies to efficiently schedule DRAM operations to reduce latency and to utilize DRAM low power modes when possible. One of the most important of these is the page policy, which determines when to close pages in DRAM. An effective DRAM memory controller page policy is important to minimizing power consumption and increasing system performance. This thesis explores the impact memory controller page policy has on performance as measured by …

Optimal Network Topologies And Resource Mappings For Heterogeneous Networks-On-Chip, Haera Chung

Dissertations and Theses

Communication has become a bottleneck for modern microprocessors and multi-core chips because metal wires don't scale. The problem becomes worse as the number of components increases and chips become bigger. Traditional Systems-on-Chips (SoCs) interconnect architectures are based on shared-bus communication, which can carry only one communication transaction at a time. This limits the communication bandwidth and scalability. Networks-on-Chip (NoC) were proposed as a promising solution for designing large and complex SoCs. The NoC paradigm provides better scalability and reusability for future SoCs, however, long-distance multi-hop communication through traditional metal wires suffers from both high latency and power consumption. A radical …

Measurement And Modeling Of Passive Surface Mount Devices On Fr4 Substrates, Rahulkumar Sadanand Koche

Dissertations and Theses

Passive components like resistors, capacitors and inductors are used in every electronic system. These are the very basic components which affect the system performance at higher frequencies and it is necessary to understand and model the behavior of these components in a very accurate manner. This work focuses on utilizing Printed Circuit Board (PCB) test boards, or fixtures, made of FR4 for characterizing Surface Mount Device (SMD) components. Agilent's Advanced Design System (ADS) microwave circuit simulation software was used for designing the microstrip transmission lines as well as for generating the layout for manufacturing of the PCB. SMD resistors, capacitors …

Dynamic Task Prediction For An Spmt Architecture Based On Control Independence, Komal Jothi

Dissertations and Theses

Exploiting better performance from computer programs translates to finding more instructions to execute in parallel. Since most general purpose programs are written in an imperatively sequential manner, closely lying instructions are always data dependent, making the designer look far ahead into the program for parallelism. This necessitates wider superscalar processors with larger instruction windows. But superscalars suffer from three key limitations, their inability to scale, sequential fetch bottleneck and high branch misprediction penalty. Recent studies indicate that current superscalars have reached the end of the road and designers will have to look for newer ideas to build computer processors.

Speculative …

A Simplified Approach To Reduce Blocking And Ringing Artifacts In Transform-Coded Images, Jianping Hu

Dissertations and Theses

Presently Block-based Discrete Cosine Transform (BDCT) image coding techniques are widely used in image and video compression applications such as JPEG and MPEG. At a moderate bit rate, BDCT is usually a quite satisfactory solution to most of practical coding applications. However, for high rate compression it produces noticeable blocking and ringing artifacts in the decompressed image. It has been an active research area for a decade for reducing these artifacts. In this thesis, a novel post-processing algorithm is proposed to remove the blocking and ringing artifacts at low bit rate. It is non-iterative and uses both spatial and transform …

Analysis And Optimization Of A Banyan Based Atm Switch By Simulations, Syed Sohel Hussain

Dissertations and Theses

Asynchronous Transfer Mode (ATM) is proposed technology to create a broadband (high speed) packet switching network capable of transporting wide variety of services including voice, video and data in an integrated manner. The main concern in designing the switching fabrics used in this technology are speed, throughput, delay and variance of delay. We analyze the performance by simulations of ATM switch based on Banyan network in the uniform traffic condition.

We compare the analytical results obtained from three-state model Yan and Jenq to the simulation results. Based on observation of simulation results, we propose non-blocking first stage (NBFS) to increase …

Ignoring Interprocessor Communication During Scheduling, Chintamani M. Patwardhan

Dissertations and Theses

The goal of parallel processing is to achieve high speed computing by partitioning a program into concurrent parts, assigning them in an efficient way to the available processors, scheduling the program and then executing the concurrent parts simultaneously. In the past researchers have combined the allocation of tasks in a program and scheduling of those tasks into one operation. We define scheduling as a process of efficiently assigning priorities to the already allocated tasks in a program. Assignment of priorities is important in cases when more than one task at a processor is ready for execution. Most heuristics for scheduling …

Parallel Architectures For Solving Combinatorial Problems Of Logic Design, Phuong Minh Ho

Dissertations and Theses

This thesis presents a new, practical approach to solve various NP-hard combinatorial problems of logic synthesis, logic programming, graph theory and related areas. A problem to be solved is polynomially time reduced to one of several generic combinatorial problems which can be expressed in the form of the Generalized Propositional Formula (GPF) : a Boolean product of clauses, where each clause is a sum of products of negated or non-negated literals.

Two Dimensional And Three Dimensional Path Planning In Robotics, Hyun Suk Kim

Dissertations and Theses

A methodology for 2D and 3D collision free path planning algorithm in a structured environment is presented. The isolated free convex areas are represented as a nodes in a graph, and a graph traversal strategy that dynamically allocates costs to graph path is used. Modification of the algorithm for small computational time and optimality is discussed. The 3D path planning is done in the three orthogonal two-dimensional projections of a 3D environment. Collision checking to increase the optimality for 3D paths is done in each of the three orthogonal two-dimensional subspaces.

Systems Reliability Using The Flow Graph, Kenneth Edward Farrier

Dissertations and Theses

The problem of calculating the reliability of a complex system of interacting elements is delineated to a linear system, no element of the system having a reliability distribution in terms of any other e1ement of the system, where only one path is taken through the system at a time. A precise definition is then developed to specify the reliability of the linear, single path at a time, system. A precise and concise generating function is found that effortlessly produces the reliability of the linear, single path at a time, system directly from the reliability flew graph of the system.