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Full-Text Articles in Computer Engineering
Deep Cellular Recurrent Neural Architecture For Efficient Multidimensional Time-Series Data Processing, Lasitha S. Vidyaratne
Deep Cellular Recurrent Neural Architecture For Efficient Multidimensional Time-Series Data Processing, Lasitha S. Vidyaratne
Electrical & Computer Engineering Theses & Dissertations
Efficient processing of time series data is a fundamental yet challenging problem in pattern recognition. Though recent developments in machine learning and deep learning have enabled remarkable improvements in processing large scale datasets in many application domains, most are designed and regulated to handle inputs that are static in time. Many real-world data, such as in biomedical, surveillance and security, financial, manufacturing and engineering applications, are rarely static in time, and demand models able to recognize patterns in both space and time. Current machine learning (ML) and deep learning (DL) models adapted for time series processing tend to grow in …
General-Purpose Digital Filter Platform, Michael Cheng
General-Purpose Digital Filter Platform, Michael Cheng
Electrical Engineering
This senior project provides a platform for high-speed, general-purpose digital filter implementation. EE 459 currently implements digital filters using reprogrammable digital signal processor boards. These aging digital signal processors serially calculate each difference equation term. Operating at 1 Mega-sample per second, the new general-purpose platform simultaneously processes at least ten digital filtering difference equation coefficients. The platform also features an audio jack input and BNC connectors for viewing input and output signals. The filter digitizes single channel audio signals at 44.1 kHz sampling rate with 16-bit precision or 1 MHz sampling at 8-bit precision. The new reprogrammable platform includes a …
Develops The Software Of Dsp Processor For The Cdma Circuitry, Arman Djohan D.
Develops The Software Of Dsp Processor For The Cdma Circuitry, Arman Djohan D.
Makara Journal of Technology
This research develops the software of DSP Processor type TMS320C54X for the CDMA circuitry. This research apply two algorithms namely Mathematic Algorithm and table lookup Algorithm. From both algorithms, the research examine what algorithm have the fasted processing time and the smallest memory occupation. From the examination results the Mathematic Algorithm have 20.62 milliseconds processing time and the Table lookup algorithm have 14.08 milliseconds processing time. The Table lookup algorithm have the fastest processing time because the Matematic algorithm need the rounding process of the fi gure. Eventhough such processing time is not exceed from the 125 millisecond of delay …
A Parallel Pipelined Computer Architecture For Digital Signal Processing, Haluk Gümüşkaya, Bülent Örenci̇k
A Parallel Pipelined Computer Architecture For Digital Signal Processing, Haluk Gümüşkaya, Bülent Örenci̇k
Turkish Journal of Electrical Engineering and Computer Sciences
This paper presents a parallel pipelined computer architecture and its six network configurations targeted for the implementation of a wide range of digital signal processing (DSP) algorithms described by both atomic and large grain data flow graphs. The proposed architecture is considered together with programmability, yielding a system solution that combines extensive concurrency with simple programming. It is an SSIMD (Skewed Single Instruction Multiple Data) or MIMD (Multiple Instruction Multiple Data) machine depending on the algorithms implemented and the programming methodologies. The concurrency that can be exploited by the algorithms using this Parallel pipelined architecture is both temporal and spatial …