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Full-Text Articles in Computer Engineering
High-Performance, Scalable Optical Network-On-Chip Architectures, Xianfang Tan
High-Performance, Scalable Optical Network-On-Chip Architectures, Xianfang Tan
UNLV Theses, Dissertations, Professional Papers, and Capstones
The rapid advance of technology enables a large number of processing cores to be integrated into a single chip which is called a Chip Multiprocessor (CMP) or a Multiprocessor System-on-Chip (MPSoC) design. The on-chip interconnection network, which is the communication infrastructure for these processing cores, plays a central role in a many-core system. With the continuously increasing complexity of many-core systems, traditional metallic wired electronic networks-on-chip (NoC) became a bottleneck because of the unbearable latency in data transmission and extremely high energy consumption on chip. Optical networks-on-chip (ONoC) has been proposed as a promising alternative paradigm for electronic NoC with …
Location Of Processor Allocator And Job Scheduler And Its Impact On Cmp Performance, Dawid Zydek, Grzegorz Chmaj, Alaa Shawky, Henry Selvaraj
Location Of Processor Allocator And Job Scheduler And Its Impact On Cmp Performance, Dawid Zydek, Grzegorz Chmaj, Alaa Shawky, Henry Selvaraj
Electrical & Computer Engineering Faculty Research
High Performance Computing (HPC) architectures are being developed continually with an aim of achieving exascale capability by 2020. Processors that are being developed and used as nodes in HPC systems are Chip Multiprocessors (CMPs) with a number of cores. In this paper, we continue our effort towards a better processor allocation process. The Processor Allocator (PA) and Job Scheduler (JS) proposed and implemented in our previous works are explored in the context of its best location on the chip. We propose a system, where all locations on a chip can be analyzed, considering energy used by Network-on-Chip (NoC), PA and …