Computer Engineering Commons^™

Facilitating Mixed Self-Timed Circuits, Alexandra R. Hanson

University Honors Theses

Designers constrain the ordering of computation events in self-timed circuits to ensure the correct behavior of the circuits. Different circuit families utilize different constraints that, when families are combined, may be more difficult to guarantee in combination without inserting delay to postpone necessary events. By analyzing established constraints of different circuit families like Click and GasP, we are able to identify the small changes necessary to either 1) avoid constraints entirely; or 2) decrease the likelihood of necessary delay insertion. Because delay insertion can be tricky for novice designers and because the likelihood of its requirement increases when mixing different …

Silicon Compilation And Test For Dataflow Implementations In Gasp And Click, Swetha Mettala Gilla

Dissertations and Theses

Many modern computer systems are distributed over space. Well-known examples are the Internet of Things and IBM's TrueNorth for deep learning applications. At the Asynchronous Research Center (ARC) at Portland State University we build distributed hardware systems using self-timed computation and delay-insensitive communication. Where appropriate, self-timed hardware operations can reduce average and peak power, energy, latency, and electromagnetic interference. Alternatively, self-timed operations can increase throughput, tolerance to delay variations, scalability, and manufacturability.

The design of complex hardware systems requires design automation and support for test, debug, and product characterization.

This thesis focuses on design compilation and test support for dataflow …

Analysis Of Parameter Tuning On Energy Efficiency In Asynchronous Circuits, Justin Thomas Roark

Graduate Theses and Dissertations

Power and energy consumption are the primary concern of the digital integrated circuit (IC) industry. Asynchronous logic, in the past several years, has increased in popularity due to its low power nature. This thesis analyzes a collection of array multipliers with different parameters to compare two asynchronous design paradigms, NULL Convention Logic (NCL) and Multi-Threshold NULL Convention Logic (MTNCL). Several commercially available pieces of software and custom scripts are used to analyze the asynchronous circuits and their components to provide the energy consumption estimation on various parts of each circuit. The analysis of the software results revealed that MTNCL circuits …

Analysis Of Error Recovery Effects On Digital Flight Control Systems, Arturo Tejada Ruiz

Electrical & Computer Engineering Theses & Dissertations

Life-critical, real-time applications like flight-by-wire aircraft, rely on closed-loop digital control systems and fault-tolerant computer systems to reliably achieve the desired operation. The computer systems, however, may be affected by random hardware/software faults induced mainly by environmental conditions such as high intensity radiated fields (HIRF) and lightning. These harsh electromagnetic environments are known to induce common­ mode faults (CMF) in aircraft electronic systems, which disrupt fault-tolerant provisions and possibly affect the operation of the digital control system. Current flight-by-wire aircraft have computer systems that can neither detect CMF nor recover from them. New systems are under investigation that can recover …

Intelligent Approaches To Vlsi Routing, Maolin Tang

Theses: Doctorates and Masters

Very Large Scale Integrated-circuit (VLSI) routing involves many large-size and complex problems and most of them have been shown to be NP-hard or NP-complete. As a result, conventional approaches, which have been successfully used to handle relatively small-size routing problems, are not suitable to be used in tackling large-size routing problems because they lead to 'combinatorial explosion' in search space. Hence, there is a need for exploring more efficient routing approaches to be incorporated into today's VLSI routing system. This thesis strives to use intelligent approaches, including symbolic intelligence and computational intelligence, to solve three VLSI routing problems: Three-Dimensional (3-D) …

Electrically Erasable Programmable Integrated Circuits For Replacement Of Obsolete Ttl Logic, Joseph V. Breen

Theses and Dissertations

Two microcircuits with electrically erasable programmable logic arrays, which use Fowler-Nordheim (F-N) tunneling for both programming and erasing, were designed to demonstrate the use of programmable logic for obsolete TTL logic replacement. Each microcircuit was fabricated in the Orbit 2-micron double-poly low noise analog CMOS process through MOSIS. Software to generate VHDL structural models from a pin list was developed and the logic of both designs was verified by simulation using the Zycad VHDL simulator. The first microcircuit included a simple programmable logic circuit and test cells that allowed measurement of the programming characteristics of the floating gate transistors. Test …