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Articles 1 - 5 of 5
Full-Text Articles in Computer Engineering
Gen-Acceleration: Pioneering Work For Hardware Accelerator Generation Using Large Language Models, Durga Lakshmi Venkata Deepak Vungarala
Gen-Acceleration: Pioneering Work For Hardware Accelerator Generation Using Large Language Models, Durga Lakshmi Venkata Deepak Vungarala
Theses
Optimizing computational power is critical in the age of data-intensive applications and Artificial Intelligence (AI)/Machine Learning (ML). While facing challenging bottlenecks, conventional Von-Neumann architecture with implementing such huge tasks looks seemingly impossible. Hardware Accelerators are critical in efficiently deploying these technologies and have been vastly explored in edge devices. This study explores a state-of-the-art hardware accelerator; Gemmini is studied; we leveraged the open-sourced tool. Furthermore, we developed a Hardware Accelerator in the study we compared with the Non-Von-Neumann architecture. Gemmini is renowned for efficient matrix multiplication, but configuring it for specific tasks requires manual effort and expertise. We propose implementing …
Remote Side-Channel Disassembly On Field-Programmable Gate Arrays, Brandon R. Baggett
Remote Side-Channel Disassembly On Field-Programmable Gate Arrays, Brandon R. Baggett
<strong> Theses and Dissertations </strong>
Over the last two decades, side-channel vulnerabilities have shown to be a major threat to embedded devices. Most side-channel research has developed our understanding of the vulnerabilities to cryptographic devices due to their implementation and how we can protect them. However, side-channel leakage can yield useful information about many other processes that run on the device. One promising area that has received little attention is the side-channel leakage due to the execution of assembly instructions. There has been some work in this area that has demonstrated the idea’s potential, but so far, this research has assumed the adversary has physical …
Accelerating Machine Learning Inference For Satellite Component Feature Extraction Using Fpgas., Andrew Ekblad
Accelerating Machine Learning Inference For Satellite Component Feature Extraction Using Fpgas., Andrew Ekblad
Theses and Dissertations
Running computer vision algorithms requires complex devices with lots of computing power, these types of devices are not well suited for space deployment. The harsh radiation environment and limited power budgets have hindered the ability of running advanced computer vision algorithms in space. This problem makes running an on-orbit servicing detection algorithm very difficult. This work proposes using a low powered FPGA to accelerate the computer vision algorithms that enable satellite component feature extraction. This work uses AMD/Xilinx’s Zynq SoC and DPU IP to run model inference. Experiments in this work centered around improving model post processing by creating implementations …
Unveiling Pain: Wearables For Objective Pain Measurement, Hanqing Tang
Unveiling Pain: Wearables For Objective Pain Measurement, Hanqing Tang
Masters Theses
">">Pain perception is a subjective experience that differs significantly among individuals, often leading to inconsistencies in assessment and management. A critical issue within this context is the gender bias in pain evaluation, which contributes to unequal treatment and perpetuates gender inequality within the healthcare system. This thesis presents an in-depth investigation of the problem and proposes the development of a wearable device for objective pain assessment. Physiological parameters — Electrocardiography (ECG) can be collected from cardiac sound signals auscultated by fabrics via nanometre-scale vibrations. Machine learning methods can accurately classify heart rate and acute pain intensity of participants. …
Digital Simulations Of Memristors Towards Integration With Reconfigurable Computing, Ivris Raymond
Digital Simulations Of Memristors Towards Integration With Reconfigurable Computing, Ivris Raymond
Computer Science and Computer Engineering Undergraduate Honors Theses
The end of Moore’s Law has been predicted for decades. Demand for increased parallel computational performance has been increased by improvements in machine learning. This past decade has demonstrated the ever-increasing creativity and effort necessary to extract scaling improvements in CMOS fabrication processes. However, CMOS scaling is nearing its fundamental physical limits. A viable path for increasing performance is to break the von Neumann bottleneck. In-memory computing using emerging memory technologies (e.g. ReRam, STT, MRAM) offers a potential path beyond the end of Moore’s Law. However, there is currently very little support from industry tools for designers wishing to incorporate …