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Full-Text Articles in Computer Engineering

A 2.56 Gbps Serial Wireline Transceiver That Supports An Auxiliary Channel And A Hybrid Line Driver To Compensate Large Channel Loss, Xiaoran Wang Aug 2020

A 2.56 Gbps Serial Wireline Transceiver That Supports An Auxiliary Channel And A Hybrid Line Driver To Compensate Large Channel Loss, Xiaoran Wang

Electrical Engineering Theses and Dissertations

Serial transceiver links are widely used for high-speed point-to-point communications. This dissertation describes two transceiver link designs for two different applications.

In serial wireline communications, security is an increasingly important factor to concern. Securing an information processing system at the application and system software layers is regarded as a necessary but incomplete defense against the cyber security threats. In this dissertation, an asynchronous serial transceiver that is capable of transmitting and receiving an auxiliary data stream concurrently with the primary data stream is described. The transceiver instantiates the auxiliary data stream by modulating the phase of the primary data without …


Formal Verification Of Divider And Square-Root Arithmetic Circuits Using Computer Algebra Methods, Atif Yasin Jul 2020

Formal Verification Of Divider And Square-Root Arithmetic Circuits Using Computer Algebra Methods, Atif Yasin

Doctoral Dissertations

A considerable progress has been made in recent years in verification of arithmetic circuits such as multipliers, fused multiply-adders, multiply-accumulate, and other components of arithmetic datapaths, both in integer and finite field domain. However, the verification of hardware dividers and square-root functions have received only a limited attention from the verification community, with a notable exception for theorem provers and other inductive, non-automated systems. Division, square root, and transcendental functions are all tied to the basic Intel architecture and proving correctness of such algorithms is of grave importance. Although belonging to the same iterative-subtract class of architectures, they widely differ …


Fitness Plug, Evan Lee Ashley Jun 2020

Fitness Plug, Evan Lee Ashley

Computer Engineering

My parents only allowed me to play videogames or watch television for a certain number of minutes or hours per day. By limiting screen time, they encouraged me to be active and find other things to do outside of television or videogames. The Fitness Plug aims to do both by converting time exercised to entertainment time; you can only watch television or play videogames for as long as you have exercised.


Otter Debugger, Keefe Johnson Jun 2020

Otter Debugger, Keefe Johnson

Computer Engineering

This project is a debugger and programmer for the OTTER CPU, the implementation of the RISC-V ISA used by Cal Poly to teach computer architecture and assembly language in CPE 233/333 and usually implemented on the Basys3 FPGA development board. With this tool, students can quickly program their OTTER with a new/revised RISC-V program binary without resynthesizing the entire FPGA design. They can then use the debugger from a PC to pause/continue/single-step execution and set breakpoints, while inspecting and modifying register and memory contents. This enables real-time debugging of OTTER projects involving custom hardware such as a keyboard and VGA …


Otter Vector Extension, Alexis A. Peralta Jun 2020

Otter Vector Extension, Alexis A. Peralta

Computer Engineering

This paper offers an implementation of a subset of the "RISC-V 'V' Vector Extension", v0.7.x. The "RISC-V 'V' Vector Extension" is the proposed vector instruction set for RISC-V open-source architecture. Vectors are inherently data-parallel, allowing for significant performance increases. Vectors have applications in fields such as cryptography, graphics, and machine learning. A vector processing unit was added to Cal Poly's RISC-V multi-cycle architecture, known as the OTTER. Computationally intensive programs running on the OTTER Vector Extension ran over three times faster when compared to the baseline multi-cycle implementation. Memory intensive applications saw similar performance increases.


Facilitating Mixed Self-Timed Circuits, Alexandra R. Hanson May 2020

Facilitating Mixed Self-Timed Circuits, Alexandra R. Hanson

University Honors Theses

Designers constrain the ordering of computation events in self-timed circuits to ensure the correct behavior of the circuits. Different circuit families utilize different constraints that, when families are combined, may be more difficult to guarantee in combination without inserting delay to postpone necessary events. By analyzing established constraints of different circuit families like Click and GasP, we are able to identify the small changes necessary to either 1) avoid constraints entirely; or 2) decrease the likelihood of necessary delay insertion. Because delay insertion can be tricky for novice designers and because the likelihood of its requirement increases when mixing different …


Analog Versus Digital Guitar Pedals, Shaping Guitar Tones And Sparking Debates, Cameron Karren May 2020

Analog Versus Digital Guitar Pedals, Shaping Guitar Tones And Sparking Debates, Cameron Karren

Capstone Projects and Master's Theses

This paper goes into the history of guitar effects, what exactly they are, how they have evolved, and what they are like today. It also presents the results of an experiment that compares perceptions of differences between analog and digital guitar pedals.


Nonlinear Least Squares 3-D Geolocation Solutions Using Time Differences Of Arrival, Michael V. Bredemann Apr 2020

Nonlinear Least Squares 3-D Geolocation Solutions Using Time Differences Of Arrival, Michael V. Bredemann

Mathematics & Statistics ETDs

This thesis uses a geometric approach to derive and solve nonlinear least squares minimization problems to geolocate a signal source in three dimensions using time differences of arrival at multiple sensor locations. There is no restriction on the maximum number of sensors used. Residual errors reach the numerical limits of machine precision. Symmetric sensor orientations are found that prevent closed form solutions of source locations lying within the null space. Maximum uncertainties in relative sensor positions and time difference of arrivals, required to locate a source within a maximum specified error, are found from these results. Examples illustrate potential requirements …


Heuristic-Based Threat Analysis Of Register-Transfer-Level Hardware Designs, Wesley Layton Ellington Apr 2020

Heuristic-Based Threat Analysis Of Register-Transfer-Level Hardware Designs, Wesley Layton Ellington

Electrical Engineering Theses and Dissertations

The development of globalized semiconductor manufacturing processes and supply chains has lead to an increased interest in hardware security as new types of hardware based attacks, called hardware Trojans, are being observed in industrial and military electronics. To combat this, a technique was developed to help analyze hardware designs at the register-transfer-level (RTL) and locate points of interest within a design that might be vulnerable to attack. This method aims to eventually enable the creation of an end-to-end design hardening solution that analyzes existing designs and suggests countermeasures for potential Trojan attacks. The method presented in this work uses a …


Design Of Hardware With Quantifiable Security Against Reverse Engineering, Shahrzad Keshavarz Mar 2020

Design Of Hardware With Quantifiable Security Against Reverse Engineering, Shahrzad Keshavarz

Doctoral Dissertations

Semiconductors are a 412 billion dollar industry and integrated circuits take on important roles in human life, from everyday use in smart-devices to critical applications like healthcare and aviation. Saving today's hardware systems from attackers can be a huge concern considering the budget spent on designing these chips and the sensitive information they may contain. In particular, after fabrication, the chip can be subject to a malicious reverse engineer that tries to invasively figure out the function of the chip or other sensitive data. Subsequent to an attack, a system can be subject to cloning, counterfeiting, or IP theft. This …


Dual-Axis Solar Tracker, Bryan Kennedy Jan 2020

Dual-Axis Solar Tracker, Bryan Kennedy

All Undergraduate Projects

Renewable energies, and fuels that are not fossil fuel-based, are one of the prolific topics of debate in modern society. With climate change now becoming a primary focus for scientists and innovators of today, one of the areas for the largest amount of potential and growth is that of the capturing and utilization of Solar Energy. This method involves using a mechanical system to track the progression of the sun as it traverses the sky throughout the day. A dual-axis solar tracker such as the one designed and built for this project, can follow the sun both azimuthally and in …


Implementation Of A Hierarchical, Embedded, Cyber Attack Detection System For Spi Devices On Unmanned Aerial Systems, Jeremy J. Price Jan 2020

Implementation Of A Hierarchical, Embedded, Cyber Attack Detection System For Spi Devices On Unmanned Aerial Systems, Jeremy J. Price

Theses and Dissertations

Unmanned Aerial Systems (UAS) create security concerns as their roles expand in commercial, military, and consumer spaces. The need to secure these systems is recognized in the architecture for a Hierarchical, Embedded, Cyber Attack Detection (HECAD) system. HECAD passively monitors the communication between a flight controller and all its peripherals like sensors and actuators. It ensures the functionality of a UAS is within the set of defined behavior and reports all potential problems, whether the errors were caused by cyber attacks or other physical faults. A portion of the design for Serial Peripheral Interface (SPI) devices on board a flight …


A Morphable Fpga Soft Processor Using Llvm Infrastructure Targeting Low-Power Application-Specific Embedded Systems, Ehsan Ali Jan 2020

A Morphable Fpga Soft Processor Using Llvm Infrastructure Targeting Low-Power Application-Specific Embedded Systems, Ehsan Ali

Chulalongkorn University Theses and Dissertations (Chula ETD)

The reconfigurable computing (RC) aims to combine the flexibility of General-Purpose Processor (GPP) with performance of Application Specific Integrated Circuits (ASIC). There are several architectures proposed since RC's inception in 1960s, but all have failed to become mainstream. The main factor preventing RC to become common practice is its requirement for implementers of algorithms (programmers) to be familiar with hardware design. In RC, a hardened processor cooperates with a dynamic reconfigurable Hardware Accelerator (HA) which is implemented on Field-Programmable Gate Array (FPGA). The HA implements crucial software kernel on hardware to increase performance and its design demands digital circuit expertise. …


Systematic Model-Based Design Assurance And Property-Based Fault Injection For Safety Critical Digital Systems, Athira Varma Jayakumar Jan 2020

Systematic Model-Based Design Assurance And Property-Based Fault Injection For Safety Critical Digital Systems, Athira Varma Jayakumar

Theses and Dissertations

With advances in sensing, wireless communications, computing, control, and automation technologies, we are witnessing the rapid uptake of Cyber-Physical Systems across many applications including connected vehicles, healthcare, energy, manufacturing, smart homes etc. Many of these applications are safety-critical in nature and they depend on the correct and safe execution of software and hardware that are intrinsically subject to faults. These faults can be design faults (Software Faults, Specification faults, etc.) or physically occurring faults (hardware failures, Single-event-upsets, etc.). Both types of faults must be addressed during the design and development of these critical systems. Several safety-critical industries have widely adopted …