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Articles 1 - 10 of 10
Full-Text Articles in Computer Engineering
Characterization Of Metal-Insulator-Transition (Mit) Phase Change Materials (Pcm) For Reconfigurable Components, Circuits, And Systems, Brent L. Danner
Characterization Of Metal-Insulator-Transition (Mit) Phase Change Materials (Pcm) For Reconfigurable Components, Circuits, And Systems, Brent L. Danner
Theses and Dissertations
Many microelectromechanical systems (MEMS) use metal contact micro-switches as part of their reconfigurable device design. These devices utilize a mechanical component that can wear down and fail over time. Metal insulator transition (MIT) materials, also known as phase change materials (PCMs), exhibit a reversible transition that can be used to replace the mechanical component in reconfigurable devices. In the presence of a thermal or electric field stimuli, the PCMs will transition back and forth between a crystalline and amorphous state. During this transformation, the resistivity, reflectivity, and Young's modulus of the material drastically change. This research effort focuses on characterizing …
Critical Information Technology On Fpgas Through Unique Device Specific Keys, Miles E. Mcgee
Critical Information Technology On Fpgas Through Unique Device Specific Keys, Miles E. Mcgee
Theses and Dissertations
Field Programmable Gate Arrays (FPGAs) are being used for military and other sensitive applications, the threat of an adversary attacking these devices is an ever present danger. While having the ability to be reconfigured is helpful for development, it also poses the risk of its hardware design being cloned. Static random access memory (SRAM) FPGA's are the most common type of FPGA used in industry. Every time an SRAM-FPGA is powered up, its configuration must be downloaded. If an adversary is able to obtain that configuration, they can clone sensitive designs to other FPGAs. A technique that can be used …
Deterministic, Efficient Variation Of Circuit Components To Improve Resistance To Reverse Engineering, Daniel F. Koranek
Deterministic, Efficient Variation Of Circuit Components To Improve Resistance To Reverse Engineering, Daniel F. Koranek
Theses and Dissertations
This research proposes two alternative methods for generating semantically equivalent circuit variants which leave the circuit's internal structure pseudo-randomly determined. Component fusion deterministically selects subcircuits using a component identification algorithm and replaces them using a deterministic algorithm that generates canonical logic forms. Component encryption seeks to alter the semantics of individual circuit components using an encoding function, but preserves the overall circuit semantics by decoding signal values later in the circuit. Experiments were conducted to examine the performance of component fusion and component encryption against representative trials of subcircuit selection-and-replacement and Boundary Blurring, two previously defined methods for circuit obfuscation. …
Performance Evaluation Of A Field Programmable Gate Array-Based System For Detecting And Tracking Peer-To-Peer Protocols On A Gigabit Ethernet Network, Brennon D. Thomas
Performance Evaluation Of A Field Programmable Gate Array-Based System For Detecting And Tracking Peer-To-Peer Protocols On A Gigabit Ethernet Network, Brennon D. Thomas
Theses and Dissertations
Recent years have seen a massive increase in illegal, suspicious, and malicious traffic traversing government and military computer networks. Some examples include illegal file distribution and disclosure of sensitive information using the BitTorrent file sharing protocol, criminals and terrorists using Voice over Internet Protocol (VoIP) technologies to communicate, and foreign entities exfiltrating sensitive data from government, military, and Department of Defense contractor networks. As a result of these growing threats, the TRacking and Analysis for Peer-to-Peer (TRAPP) system was developed in 2008 to detect BitTorrent and VoIP traffic of interest. The TRAPP system, designed on a Xilinx Virtex-II Pro Field …
High Power Microwave (Hpm) And Ionizing Radiation Effects On Cmos Devices, Nicholas A. Estep
High Power Microwave (Hpm) And Ionizing Radiation Effects On Cmos Devices, Nicholas A. Estep
Theses and Dissertations
Integrated circuits (ICs) are inherently complicated and made worse by increasing transistor quantity and density. This trend potentially enhances concomitant effects of high energy radiation and local or impressed electromagnetic interference (EMI). The reduced margin for signal error may counter any gain in radiation hardness from smaller device dimensions. Isolated EMI and ionizing radiation studies on circuits have been conducted extensively over the past 30 years. However, little focus has been placed on the combined effects. To investigate the effect of combined EMI and ionizing radiation, two complementary metal oxide semiconductor (CMOS) inverter technologies (CD4069 and SN74AUC1G04) were analyzed for …
Chip To Chip Optical Interconnection Using Mems Mirrors, Tod V. Laurvick
Chip To Chip Optical Interconnection Using Mems Mirrors, Tod V. Laurvick
Theses and Dissertations
This experiment explores the use of MEMS mirrors to direct subsurface optical signals to another device and reception of those signals for use in chip to chip communications. Devices were built in PolyMUMPs to control horizontal and vertical beam direction and tilting in the outgoing signal and MEMS beam splitters for the incoming signal. Several elements of the outgoing beam path were successful and those which needed improvement indicate a high probability of success with limited trials needed and currently successful design elements could still be improved within the scope of PolyMUMPs. The incoming beam path elements were not successful …
Evaluation Of A Field Programmable Gate Array Circuit Reconfiguration System, Jason L. Ives
Evaluation Of A Field Programmable Gate Array Circuit Reconfiguration System, Jason L. Ives
Theses and Dissertations
This research implements a circuit reconfiguration system (CRS) to reconfigure a field programmable gate array (FPGA) in response to a faulty configurable logic block (CLB). It is assumed that the location of the fault is known and the CLB is moved according to one of four replacement methods: column left, column right, row up, and row down. Partial reconfiguration of the FPGA is done through the Joint Test Action Group (JTAG) port to produce the desired logic block movement. The time required to accomplish the reconfiguration is measured for each method in both clear and congested areas of the FPGA. …
Boolean Reasoning And Informed Search In The Minimization Of Logic Circuits, James J. Kainec
Boolean Reasoning And Informed Search In The Minimization Of Logic Circuits, James J. Kainec
Theses and Dissertations
The minimization of logic circuits has been an important area of research for more than a half century. The approaches taken in this field, however, have for the most part been ad hoc. Boolean techniques have been employed to manipulate formulas, but not to perform symbolic reasoning. Boolean equations are employed principally as icons; they are never solved. The first objective of this dissertation is to apply Boolean reasoning systematically and uniformly to the minimization problem. Boolean reasoning entails the reduction of systems of Boolean equations to a single equation; the single equation is an abstraction, independent of the form …
Electrically Erasable Programmable Integrated Circuits For Replacement Of Obsolete Ttl Logic, Joseph V. Breen
Electrically Erasable Programmable Integrated Circuits For Replacement Of Obsolete Ttl Logic, Joseph V. Breen
Theses and Dissertations
Two microcircuits with electrically erasable programmable logic arrays, which use Fowler-Nordheim (F-N) tunneling for both programming and erasing, were designed to demonstrate the use of programmable logic for obsolete TTL logic replacement. Each microcircuit was fabricated in the Orbit 2-micron double-poly low noise analog CMOS process through MOSIS. Software to generate VHDL structural models from a pin list was developed and the logic of both designs was verified by simulation using the Zycad VHDL simulator. The first microcircuit included a simple programmable logic circuit and test cells that allowed measurement of the programming characteristics of the floating gate transistors. Test …
Parallel Implementation Of Vhdl Simulations On The Intel Ipsc/2 Hypercube, Ronald C. Comeau
Parallel Implementation Of Vhdl Simulations On The Intel Ipsc/2 Hypercube, Ronald C. Comeau
Theses and Dissertations
VHDL models are executed sequentially in current commercial simulators. As chip designs grow larger and more complex, simulations must run faster. One approach to increasing simulation speed is through parallel processors. This research transforms the behavioral and structural models created by Intermetrics' sequential VHDL simulator into models for parallel execution. The models are simulated on an Intel iPSC/2 hypercube with synchronization of the nodes being achieved by utilizing the Chandy Misra paradigm for discrete-event simulations. Three eight-bit adders, the ripple carry, the carry save, and the carry-lookahead, are each run through the parallel simulator. Simulation time is cut in at …