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Full-Text Articles in Computer Engineering
A Compiler Target Model For Line Associative Registers, Paul S. Eberhart
A Compiler Target Model For Line Associative Registers, Paul S. Eberhart
Theses and Dissertations--Electrical and Computer Engineering
LARs (Line Associative Registers) are very wide tagged registers, used for both register-wide SWAR (SIMD Within a Register )operations and scalar operations on arbitrary fields. LARs include a large data field, type tags, source addresses, and a dirty bit, which allow them to not only replace both caches and registers in the conventional memory hierarchy, but improve on both their functions. This thesis details a LAR-based architecture, and describes the design of a compiler which can generate code for a LAR-based design. In particular, type conversion, alignment, and register allocation are discussed in detail.
Modifying Instruction Sets In The Gem5 Simulator To Support Fault Tolerant Designs, Chuan Zhang
Modifying Instruction Sets In The Gem5 Simulator To Support Fault Tolerant Designs, Chuan Zhang
Masters Theses
Traditional fault tolerant techniques such as hardware or time redundancy incur high overhead and are inefficient for checking arithmetic operations. Our objective is to study an alternative approach of adding new instructions to check arithmetic operations. These checking instructions either rely on error detecting code or calculate approximate results and consequently, consume much less execution time. To evaluate the effectiveness of such an approach we wish to modify several benchmarks to use checking instructions and run simulation experiments to find out their execution time and memory usage. However, the checking instructions are not included in the instruction set and as …
An Investigation Into Partitioning Algorithms For Automatic Heterogeneous Compilers, Antonio M. Leija
An Investigation Into Partitioning Algorithms For Automatic Heterogeneous Compilers, Antonio M. Leija
Master's Theses
Automatic Heterogeneous Compilers allows blended hardware-software solutions to be explored without the cost of a full-fledged design team, but limited research exists on current partitioning algorithms responsible for separating hardware and software. The purpose of this thesis is to implement various partitioning algorithms onto the same automatic heterogeneous compiler platform to create an apples to apples comparison for AHC partitioning algorithms. Both estimated outcomes and actual outcomes for the solutions generated are studied and scored. The platform used to implement the algorithms is Cal Poly’s own Twill compiler, created by Doug Gallatin last year. Twill’s original partitioning algorithm is chosen …
Compacting Loads And Stores For Code Size Reduction, Isaac Asay
Compacting Loads And Stores For Code Size Reduction, Isaac Asay
Master's Theses
It is important for compilers to generate executable code that is as small as possible, particularly when generating code for embedded systems. One method of reducing code size is to use instruction set architectures (ISAs) that support combining multiple operations into single operations. The ARM ISA allows for combining multiple memory operations to contiguous memory addresses into a single operation. The LLVM compiler contains a specific memory optimization to perform this combining of memory operations, called ARMLoadStoreOpt. This optimization, however, relies on another optimization (ARMPreAllocLoadStoreOpt) to move eligible memory operations into proximity in order to perform properly. This mover optimization …