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Full-Text Articles in Computer Engineering
Power-Efficient And Low-Latency Memory Access For Cmp Systems With Heterogeneous Scratchpad On-Chip Memory, Zhi Chen
Theses and Dissertations--Electrical and Computer Engineering
The gradually widening speed disparity of between CPU and memory has become an overwhelming bottleneck for the development of Chip Multiprocessor (CMP) systems. In addition, increasing penalties caused by frequent on-chip memory accesses have raised critical challenges in delivering high memory access performance with tight power and latency budgets. To overcome the daunting memory wall and energy wall issues, this thesis focuses on proposing a new heterogeneous scratchpad memory architecture which is configured from SRAM, MRAM, and Z-RAM. Based on this architecture, we propose two algorithms, a dynamic programming and a genetic algorithm, to perform data allocation to different memory …
Fpga-Based Implementation Of Dual-Frequency Pattern Scheme For 3-D Shape Measurement, Brent Bondehagen
Fpga-Based Implementation Of Dual-Frequency Pattern Scheme For 3-D Shape Measurement, Brent Bondehagen
Theses and Dissertations--Electrical and Computer Engineering
Structured Light Illumination (SLI) is the process where spatially varied patterns are projected onto a 3-D surface and based on the distortion by the surface topology, phase information can be calculated and a 3D model constructed. Phase Measuring Profilometry (PMP) is a particular type of SLI that requires three or more patterns temporarily multiplexed. High speed PMP attempts to scan moving objects whose motion is small so as to have little impact on the 3-D model. Given that practically all machine vision cameras and high speed cameras employ a Field Programmable Gate Array (FPGA) interface directly to the image sensors, …
A Comprehensive Hdl Model Of A Line Associative Register Based Architecture, Matthew A. Sparks
A Comprehensive Hdl Model Of A Line Associative Register Based Architecture, Matthew A. Sparks
Theses and Dissertations--Electrical and Computer Engineering
Modern processor architectures suffer from an ever increasing gap between processor and memory performance. The current memory-register model attempts to hide this gap by a system of cache memory. Line Associative Registers(LARs) are proposed as a new system to avoid the memory gap by pre-fetching and associative updating of both instructions and data. This thesis presents a fully LAR-based architecture, targeting a previously developed instruction set architecture. This architecture features an execution pipeline supporting SWAR operations, and a memory system supporting the associative behavior of LARs and lazy writeback to memory.