Computer Engineering Commons^™

Novel Architecture Of Onem2m-Based Convergence Platform For Mixed Reality And Iot, Seungwoon Lee, Woogeun Kil, Byeong Hee Roh, Si-Jung Kim, Jin Suk Kang

College of Engineering Faculty Research

There have been numerous works proposed to merge augmented reality/mixed reality (AR/MR) and Internet of Things (IoT) in various ways. However, they have focused on their specific target applications and have limitations on interoperability or reusability when utilizing them to different domains or adding other devices to the system. This paper proposes a novel architecture of a convergence platform for AR/MR and IoT systems and services. The proposed architecture adopts the oneM2M IoT standard as the basic framework that converges AR/MR and IoT systems and enables the development of application services used in general-purpose environments without being subordinate to specific …

Design And Implementation Of An Instruction Set Architecture And An Instruction Execution Unit For The Rez9 Coprocessor System, Daniel Spencer Anderson

UNLV Theses, Dissertations, Professional Papers, and Capstones

While the use of RNS has provided groundbreaking theory and progress in this field, the applications still lack viable testing platforms to test and verify the theory. This Thesis outlines the processing of developing an instruction set architecture (ISA) and an instruction execution unit (IEU) to help make the first residue based general processor a viable testing platform to address the mentioned problems.

Consider a 32-bit ripple adder. The delay on this device will be 32N where N is the delay for each adder to complete its operation. The delay of this process is due to the need to propagate …

On High-Performance Parallel Fixed-Point Decimal Multiplier Designs, Ming Zhu

UNLV Theses, Dissertations, Professional Papers, and Capstones

High-performance, area-efficient hardware implementation of decimal multiplication is preferred to slow software simulations in a number of key scientific and financial application areas, where errors caused by converting decimal numbers into their approximate binary representations are not acceptable.

Multi-digit parallel decimal multipliers involve two major stages: (i) the partial product generation (PPG) stage, where decimal partial products are determined by selecting the right versions of the pre-computed multiples of the multiplicand, followed by (ii) the partial product accumulation (PPA) stage, where all the partial products are shifted and then added together to obtain the final multiplication product. In this thesis, …

High-Performance, Scalable Optical Network-On-Chip Architectures, Xianfang Tan

UNLV Theses, Dissertations, Professional Papers, and Capstones

The rapid advance of technology enables a large number of processing cores to be integrated into a single chip which is called a Chip Multiprocessor (CMP) or a Multiprocessor System-on-Chip (MPSoC) design. The on-chip interconnection network, which is the communication infrastructure for these processing cores, plays a central role in a many-core system. With the continuously increasing complexity of many-core systems, traditional metallic wired electronic networks-on-chip (NoC) became a bottleneck because of the unbearable latency in data transmission and extremely high energy consumption on chip. Optical networks-on-chip (ONoC) has been proposed as a promising alternative paradigm for electronic NoC with …

On High-Performance Parallel Decimal Fixed-Point Multiplier Designs, Ming Zhu

College of Engineering: Graduate Celebration Programs

Decimal computations are required in finance, and etc.

• Precise representation for decimals (E.g. 0.2, 0.7… )
• Performance Requirements (Software simulations are very slow)

A P2p Computing System For Overlay Networks, Grzegorz Chmaj, Krzysztof Walkowiak

Electrical & Computer Engineering Faculty Research

A distributed computing system is able to perform data computation and distribution of results at the same time. The input task is divided into blocks, which are then sent to system participants that offer their resources in order to perform calculations. Next, a partial result is sent back by the participants to the task manager (usually one central node). In the case when system participants want to get the final result, the central node may become overloaded, especially if many nodes request the result at the same time. In this paper we propose a novel distributed computation system, which does …

Heuristic Algorithms For Optimization Of Task Allocation And Result Distribution In Peer-To-Peer Computing Systems, Grzegorz Chmaj, Krzysztof Walkowiak, Michal Tarnawski, Michal Kucharzak

Electrical & Computer Engineering Faculty Research

Recently, distributed computing system have been gaining much attention due to a growing demand for various kinds of effective computations in both industry and academia. In this paper, we focus on Peer-to-Peer (P2P) computing systems, also called public-resource computing systems or global computing systems. P2P computing systems, contrary to grids, use personal computers and other relatively simple electronic equipment (e.g., the PlayStation console) to process sophisticated computational projects. A significant example of the P2P computing idea is the BOINC (Berkeley Open Infrastructure for Network Computing) project. To improve the performance of the computing system, we propose to use the P2P …

Cpu Scheduling For Power/Energy Management On Heterogeneous Multicore Processors, Rajesh Patel

UNLV Theses, Dissertations, Professional Papers, and Capstones

Power and energy have become increasingly important concerns in the design and implementation of today's multicore/manycore chips. Many methods have been proposed to reduce a microprocessor's power usage and associated heat dissipation, including scaling a core's operating frequency. However, these techniques do not consider the dynamic performance characteristics of an executing process at runtime, the execution characteristics of the entire task to which this process belongs, the process's priority, the process's cache miss/cache reference ratio, the number of context switches and CPU migrations generated by the process, nor the system load. Also, many of the techniques that employ dynamic frequency …

Decimal Alu, Ming Zhu

College of Engineering: Graduate Celebration Programs

The decimal number system is used in many commercial applications, such as financial analysis, banking, tax calculation, currency conversion, insurance and accounting. With the explosively increasing amount the data to be proposed, computers are introduced to help deal with it. However, in digital Arithmetic Logic Unit (ALU) circuit systems, the binary number system is widely used for its simplicity and easy realization in physical layout. This project aims at constructing an ALU that contains decimal additions, subtractions and multiplications using binary coded decimal (BCD) on a binary system platform.

Location Of Processor Allocator And Job Scheduler And Its Impact On Cmp Performance, Dawid Zydek, Grzegorz Chmaj, Alaa Shawky, Henry Selvaraj

Electrical & Computer Engineering Faculty Research

High Performance Computing (HPC) architectures are being developed continually with an aim of achieving exascale capability by 2020. Processors that are being developed and used as nodes in HPC systems are Chip Multiprocessors (CMPs) with a number of cores. In this paper, we continue our effort towards a better processor allocation process. The Processor Allocator (PA) and Job Scheduler (JS) proposed and implemented in our previous works are explored in the context of its best location on the chip. We propose a system, where all locations on a chip can be analyzed, considering energy used by Network-on-Chip (NoC), PA and …

Decision Strategies For A P2p Computing System, Grzegorz Chmaj, Krzysztof Walkowiak

Electrical & Computer Engineering Faculty Research

Peer-to-Peer (P2P) computing (also called ‘public-resource computing’) is an effective approach to perform computation of large tasks. Currently used P2P computing systems (e.g., BOINC) are most often centrally managed, i.e., the final result of computations is created at a central node using partial results – what may be not efficient in the case when numerous participants are willing to download the final result. In this paper, we propose a novel approach to P2P computing systems. We assume that results can be delivered to all peers in a distributed way using three types of network flows: unicast, Peer-to-Peer and anycast. We …

Software Development Approach For Discrete Simulators, Grzegorz Chmaj, Dawid Maksymilian Zydek

Electrical & Computer Engineering Faculty Research

Simulation is the most common approach to perform the problem research. Among several types of simulation, the most common way is the discrete simulation, which assumes the division of the time scale into fixed length time slots. Depending on investigated problem, simulation packages may be used or it could be necessary to design and create own simulation system. In this paper, we propose the complete pre-study scheme and the most commonly appearing implementation problems with suggested solutions. We also describe how to implement the exemplary simulator in C++.

Optical Network-On-Chip Architectures And Designs, Lei Zhang

UNLV Theses, Dissertations, Professional Papers, and Capstones

As indicated in the latest version of ITRS roadmap, optical wiring is a viable interconnection technology for future SoC/SiC/SiP designs that can provide broad band data transfer rates unmatchable by the existing metal/low-k dielectric interconnects. In this dissertation study, a set of different optical interconnection architectures are presented for future on-chip optical micro-networks.

Three Optical Network-on-Chip (ONoC) architectures, i.e., Wavelength Routing Optical Network-on-Chip (WRON), Redundant Wavelength Routed Optical Network (RDWRON) and Recursive Wavelength Routed Optical Network (RCWRON) are proposed. They are fully connected networks designed based on passive switching Microring Resonator (MRR) optical switches. Given enough different routing optical wavelengths, …

Data Routing In Multicore Processors Using Dimension Increment Method, Arpita H. Kadakia

UNLV Theses, Dissertations, Professional Papers, and Capstones

A Deadlock-free routing algorithm can be generated for arbitrary interconnection network using the concept of virtual channels but the virtual channels will lead to more complex algorithms and more demands of NOC resource.

In this thesis, we study a Torus topology for NOC application, design its structure and propose a routing algorithm exploiting the characteristics of NOC. We have chosen a typical 16 (4 by 4) routers Torus and propose the corresponding route algorithm. In our algorithm, all the channels are assigned 4 different dimensions (n0,n1,n2 & n3). By following the dimension increment method, we break the dependent route circles, …

Dynamic Distributed Programming And Applications To Swap Edge Problem, Feven Z. Andemeskel

UNLV Theses, Dissertations, Professional Papers, and Capstones

Link failure is a common reason for disruption in communication networks. If communication between processes of a weighted distributed network is maintained by a spanning tree T, and if one edge e of T fails, communication can be restored by finding a new spanning tree, T’. If the network is 2-edge connected, T’ can always be constructed by replacing e by a single edge, e’, of the network. We refer to e’ as a swap edge of e.

The best swap edge problem is to find the best choice of e’, that is, that e which causes the new spanning …

Processor Allocator For Chip Multiprocessors, Dawid Maksymilian Zydek

UNLV Theses, Dissertations, Professional Papers, and Capstones

Chip MultiProcessor (CMP) architectures consisting of many cores connected through Network-on-Chip (NoC) are becoming main computing platforms for research and computer centers, and in the future for commercial solutions. In order to effectively use CMPs, operating system is an important factor and it should support a multiuser environment in which many parallel jobs are executed simultaneously. It is done by the processor management system of the operating system, which consists of two components: Job Scheduler (JS) and Processor Allocator (PA). The JS is responsible for job scheduling that deals with selection of the next job to be executed, while the …

Random Approach To Optimization Of Overlay Public-Resource Computing Systems, Grzegorz Chmaj, Krzysztof Walkowiak

Electrical & Computer Engineering Faculty Research

The growing need for computationally demanding systems triggers the development of various network-oriented computing systems organized in a distributed manner. In this work we concentrate on one kind of such systems, i.e. public-resource computing systems. The considered system works on the top of an overlay network and uses personal computers and other relatively simple electronic equipment instead of supercomputers. We assume that two kinds of network flows are used to distribute the data in the public-resource computing systems: unicast and peer-to-peer. We formulate an optimization model of the system. After that we propose random algorithms that optimize jointly the allocation …

Networking And Computing Infrastructure In Nevada: Current Status And Future Developments, Frederick C. Harris

2010 Annual Nevada NSF EPSCoR Climate Change Conference

12 PowerPoint slides Session 2: Infrastructure Convener: Sergiu Dascalu, UNR

Architecture And Usability Aspects Of Environmental Data Portals, Michael Mcmahon, Jr.

2010 Annual Nevada NSF EPSCoR Climate Change Conference

12 PowerPoint slides Session 2: Infrastructure Convener: Sergiu Dascalu, UNR Abstract: -Web Portal: A web site that acts as a starting point or gateway to Internet content, services, and information. Portals expose this information via a consistent set of visual elements and organizational constructs that improve the user experience and may relate, unify, or otherwise enhance the content. -Data Portal: A web site that acts as a starting point or gateway to Internet content, web/data services, and related information. Portals expose this information via a consistent set of visual elements and organizational constructs that improve the user experience and relate, …

Research Poster: Architecture And Usability Aspects Of Environmental Data Portals, Victor Ivanov

2010 Annual Nevada NSF EPSCoR Climate Change Conference

Research poster

Research Poster: Htsma: A Hybrid Temporal-Spatial Multi-Channel Assignment Scheme In Heterogeneous Wireless Mesh Networks, Yan Jin, Ju-Yeon Jo, Mei Yang, Yoohwan Kim, Yingtao Jiang, John Gowens

2010 Annual Nevada NSF EPSCoR Climate Change Conference

Research poster

Research Poster: Survey Of Environmental Data Portals: Features And Characteristics, David Walker

2010 Annual Nevada NSF EPSCoR Climate Change Conference

Research poster

Scheduling Architectures For Diffserv Networks With Input Queuing Switches, Mei Yang, Henry Selvaraj, Enyue Lu, Jianping Wang, S. Q. Zheng, Yingtao Jiang

Electrical & Computer Engineering Faculty Research

ue to its simplicity and scalability, the differentiated services (DiffServ) model is expected to be widely deployed across wired and wireless networks. Though supporting DiffServ scheduling algorithms for output-queuing (OQ) switches have been widely studied, there are few DiffServ scheduling algorithms for input-queuing (IQ) switches in the literaure. In this paper, we propose two algorithms for scheduling DiffServ DiffServ networks with IQ switches: the dynamic DiffServ scheduling (DDS) algorithm and the hierarchical DiffServ scheduling (HDS) algorithm. The basic idea of DDS and HDS is to schedule EF and AF traffic According to Their minimum service rates with the reserved bandwidth …

Preliminary Study On Optimization Of Data Distribution In Resource Sharing Systems, Grzegorz Chmaj, Krzysztof Walkowiak

Electrical & Computer Engineering Faculty Research

Grid structures are increasingly considered as very convergent with peer-to-peer networks. This paper presents a model of network acting both as grid and peer-to-peer network, used for data computation and distribution. Presented PPLC algorithm is a complete solution for both grid and peer-to-peer points of view. Problem formulation is presented, as well as solution heuristic algorithm and research results.

Nesting System With Quantization And Knowledge Base Applied, Leszek Koszalka, Grzegorz Chmaj

Electrical & Computer Engineering Faculty Research

Nesting algorithms deal with placing two dimensional shapes on the given canvas. In this paper a binary way of solving the nesting problem is proposed. Geometric shapes are quantized into binary form, which is used to operate on them. After finishing nesting they are converted back into original geometrical form. Investigations showed, that there is a big influence of quantization accuracy for the nesting effect. However, greater accuracy results with longer time of computation. The proposed knowledge base system is able to strongly reduce the computational time.

Efficient Scheduling For Sdmg Cioq Switches, Mei Yang, S. Q. Zheng

Electrical & Computer Engineering Faculty Research

Combined input and output queuing (CIOQ) switches are being considered as high-performance switch architectures due to their ability to achieve 100% throughput and perfectly emulate output queuing (OQ) switch performance with a small speedup factor S. To realize a speedup factor S, a conventional CIOQ switch requires the switching fabric and memories to operate S times faster than the line rate. In this paper, we propose to use a CIOQ switch with space-division multiplexing expansion and grouped input/output ports (SDMG CIOQ switch for short) to realize speedup while only requiring the switching fabric and memories to operate at the line …