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Full-Text Articles in Computer Engineering
Design Of Area-Efficient Iir Filter Using Fppe, Ramyarani Nallathambi, Subbiah Veerana, Deepa Prabhakaran
Design Of Area-Efficient Iir Filter Using Fppe, Ramyarani Nallathambi, Subbiah Veerana, Deepa Prabhakaran
Turkish Journal of Electrical Engineering and Computer Sciences
Floating point arithmetic circuits provide wide dynamic range and high precision, and they are widely used in scientific computing and signal processing applications, but the complexity increases in hardware implementations of floating point units. In VLSI design architecture, many applications suffer in size of the components used in logical operations. The aim of reducing architecture is to gain reduction in power loss and also in area, but the reduction in size of the components leads to an increase in delay and memory. Hence, to overcome these limitations and to optimize the area, a novel design of floating point processing element …
Performance Analysis And Optimization Of Cluster-Based Mesh Fpga Architectures: Design Methodology And Cad Tool Support, Sonda Chtourou, Zied Marrakchi, Emna Amouri, Vinod Pangracious, Mohamed Abid, Habib Mehrez
Performance Analysis And Optimization Of Cluster-Based Mesh Fpga Architectures: Design Methodology And Cad Tool Support, Sonda Chtourou, Zied Marrakchi, Emna Amouri, Vinod Pangracious, Mohamed Abid, Habib Mehrez
Turkish Journal of Electrical Engineering and Computer Sciences
Field programmable gate arrays (FPGAs) have become an attractive implementation medium for digital circuits. FPGA design's big challenge is to find a good trade-off between flexibility and performance in terms of power dissipation, area density, and delay. This paper presents a new cluster-based FPGA architecture combining mesh and hierarchical interconnect topologies. Based on experimental method and benchmarks circuit implementation, this work provides a detailed exploration and analyses of the effect of cluster functionality on the proposed cluster-based FPGA in terms of power dissipation, area density, and delay. The exploration results showed that architecture with high cluster size provides high speed …
Novel Dynamic Partial Reconfiguration Implementations Of The Support Vector Machine Classifier On Fpga, Hanaa Hussain, Khaled Benkrid, Hüseyi̇n Şeker
Novel Dynamic Partial Reconfiguration Implementations Of The Support Vector Machine Classifier On Fpga, Hanaa Hussain, Khaled Benkrid, Hüseyi̇n Şeker
Turkish Journal of Electrical Engineering and Computer Sciences
The support vector machine (SVM) is one of the highly powerful classifiers that have been shown to be capable of dealing with high-dimensional data. However, its complexity increases requirements of computational power. Recent technologies including the postgenome data of high-dimensional nature add further complexity to the construction of SVM classifiers. In order to overcome this problem, hardware implementations of the SVM classifier have been proposed to benefit from parallelism to accelerate the SVM. On the other hand, those implementations offer limited flexibility in terms of changing parameters and require the reconfiguration of the whole device. The latter interrupts the operation …
Performance Evaluation Of A New Efficient H.264 Intraprediction Scheme, Sara Hamdy, Mostafa Ibrahim, Mohamed Osman
Performance Evaluation Of A New Efficient H.264 Intraprediction Scheme, Sara Hamdy, Mostafa Ibrahim, Mohamed Osman
Turkish Journal of Electrical Engineering and Computer Sciences
The paper presents a new efficient H.264/AVC$ 4 \times 4$ intraprediction scheme. The new prediction scheme is based on the best prediction matrix mode. The main idea behind the new prediction scheme is to combine the most usable intraprediction modes, {vertical - horizontal - DC} , into a new efficient prediction mode. The new prediction scheme is implemented using VHDL and hence it uses the full advantages of inherent parallelism in the hardware. We evaluate the performance of this prediction scheme in terms of compression ratio, peak signal to noise ratio, and bit rate using seven video sequences. Moreover, we …
A Comparative Study Of Two Different Fpga-Based Arrhythmia Classifier Architectures, Ahmet Turan Özdemi̇r, Kenan Danişman
A Comparative Study Of Two Different Fpga-Based Arrhythmia Classifier Architectures, Ahmet Turan Özdemi̇r, Kenan Danişman
Turkish Journal of Electrical Engineering and Computer Sciences
Early diagnosis of dangerous heart conditions is very important for the treatment of heart diseases and for the prevention of sudden cardiac death. Automatic electrocardiogram (ECG) arrhythmia classifiers are essential to timely diagnosis. However, most of the medical diagnosis systems proposed in the literature are software-based. This work focused on the hardware implementation of a mobile artificial neural network (ANN)-based arrhythmia classifier that is implemented on a field programmable gate array (FPGA) as a single chip solution, as an alternative to various software models of ANNs. Due to the parallel nature of ANNs, hardware implementation of ANNs needs a large …
Fully Parallel Ann-Based Arrhythmia Classifier On A Single-Chip Fpga: Fpaac, Ahmet Turan Özdemi̇r, Kenan Danişman
Fully Parallel Ann-Based Arrhythmia Classifier On A Single-Chip Fpga: Fpaac, Ahmet Turan Özdemi̇r, Kenan Danişman
Turkish Journal of Electrical Engineering and Computer Sciences
Recognition of cardiac arrhythmias by electrocardiogram (ECG) is an important issue for diagnosis of cardiac abnormalities. Many studies on recognition of cardiac arrhythmias by ECG, using various techniques, have been performed in the past 20 years. Artificial neural networks (ANNs) are the most widely used tool in medical diagnosis systems (MDS) because of their powerful prediction characteristics. An ANN model is inspired by real biological neural networks, with a parallel structure that is potentially fast for computation. However, the suggested ANN architectures in the literature can only be run sequentially, on powerful processors, due to their complexity. Our approach enables …