Open Access. Powered by Scholars. Published by Universities.®

Computer Engineering Commons

Open Access. Powered by Scholars. Published by Universities.®

Articles 1 - 5 of 5

Full-Text Articles in Computer Engineering

Post Processing Of Optically Recognized Text Using First Order Hidden Markov Model, Spandana Malreddy Dec 2012

Post Processing Of Optically Recognized Text Using First Order Hidden Markov Model, Spandana Malreddy

UNLV Theses, Dissertations, Professional Papers, and Capstones

In this thesis, we report on our design and implementation of a post processing system for Optically Recognized text. The system is based on first order Hidden Markov Model (HMM). The Maximum Likelihood algorithm is used to train the system with over 150 thousand characters. The system is also tested on a file containing 5688 characters. The percentage of errors detected and corrected is 11.76% with a recall of 10.16% and precision of 100%


Hardware-Software Co-Design, Acceleration And Prototyping Of Control Algorithms On Reconfigurable Platforms, Desta Kumsa Edosa Dec 2012

Hardware-Software Co-Design, Acceleration And Prototyping Of Control Algorithms On Reconfigurable Platforms, Desta Kumsa Edosa

UNLV Theses, Dissertations, Professional Papers, and Capstones

Differential equations play a significant role in many disciplines of science and engineering. Solving and implementing Ordinary Differential Equations (ODEs) and partial Differential Equations (PDEs) effectively are very essential as most complex dynamic systems are modeled based on these equations. High Performance Computing (HPC) methodologies are required to compute and implement complex and data intensive applications modeled by differential equations at higher speed. There are, however, some challenges and limitations in implementing dynamic system, modeled by non-linear ordinary differential equations, on digital hardware. Modeling an integrator involves data approximation which results in accuracy error if data values are not considered …


Non-Blocking Concurrent Operations On Heap, Mahesh Acharya Aug 2012

Non-Blocking Concurrent Operations On Heap, Mahesh Acharya

UNLV Theses, Dissertations, Professional Papers, and Capstones

We present a non-blocking implementation for the concurrent Heap data structure in the asynchronous shared memory system. The system may be a traditional one with a single processor with multiple threads, or it may be the one with multiple processors each possibly with multiple threads. Our implementation supports readMin, deleteMin, and insert operations on the heap. The deleteMin and insert operations are non-blocking operations, whereas the readMin is wait-free. One easy approach of using a heap in multi-threading environment could be by locking the entire heap before performing any operation. This would make the implementation very slow to have any …


Node Filtering And Face Routing For Sensor Network, Umang Amatya Aug 2012

Node Filtering And Face Routing For Sensor Network, Umang Amatya

UNLV Theses, Dissertations, Professional Papers, and Capstones

Greedy forward routing and face routing algorithms have been extensively used for sending messages in sensor networks. In this thesis, we consider the problem of filtering redundant nodes in a sensor network as a pre-processing step for face routing. We propose two algorithms for identifying redundant nodes. We test the performance of proposed filtering algorithms on generated networks. The prototype algorithm for testing the proposed algorithms has been implemented in the Java programming language. Experimental investigation shows that the proposed filtering algorithms are effective in removing redundant nodes without compromising the network connectivity.


Cpu Scheduling For Power/Energy Management On Heterogeneous Multicore Processors, Rajesh Patel Aug 2012

Cpu Scheduling For Power/Energy Management On Heterogeneous Multicore Processors, Rajesh Patel

UNLV Theses, Dissertations, Professional Papers, and Capstones

Power and energy have become increasingly important concerns in the design and implementation of today's multicore/manycore chips. Many methods have been proposed to reduce a microprocessor's power usage and associated heat dissipation, including scaling a core's operating frequency. However, these techniques do not consider the dynamic performance characteristics of an executing process at runtime, the execution characteristics of the entire task to which this process belongs, the process's priority, the process's cache miss/cache reference ratio, the number of context switches and CPU migrations generated by the process, nor the system load. Also, many of the techniques that employ dynamic frequency …