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Full-Text Articles in Computer Engineering
Modeling And Architectural Simulations Of The Statistical Static Timing Analysis Of The Variation Sources For Vlsi Circuits, Abu M. Baker
Modeling And Architectural Simulations Of The Statistical Static Timing Analysis Of The Variation Sources For Vlsi Circuits, Abu M. Baker
College of Engineering: Graduate Celebration Programs
As CMOS technology scales down, process variation introduces significant uncertainty in power and performance to VLSI circuits and significantly affects their reliability. Although Static-Timing Analysis (STA) remains an excellent tool, current trends in process scaling have imposed significant difficulties to STA. As one of the promising solutions, Statistical static timing analysis (SSTA) has become the frontier research topic in recent years in combating such variation effects. This poster will be focusing on two aspects of SSTA and its applications in VLSI designs: (1) Statistical timing modeling and analysis; and (2) Architectural implementations of the atomic operations (max and add) using …
Non-Blocking Concurrent Operations On Heap, Mahesh Acharya
Non-Blocking Concurrent Operations On Heap, Mahesh Acharya
UNLV Theses, Dissertations, Professional Papers, and Capstones
We present a non-blocking implementation for the concurrent Heap data structure in the asynchronous shared memory system. The system may be a traditional one with a single processor with multiple threads, or it may be the one with multiple processors each possibly with multiple threads. Our implementation supports readMin, deleteMin, and insert operations on the heap. The deleteMin and insert operations are non-blocking operations, whereas the readMin is wait-free. One easy approach of using a heap in multi-threading environment could be by locking the entire heap before performing any operation. This would make the implementation very slow to have any …