Engineering Commons^™

Design On High Performance Nanoscale Cmos Circuits With Low Temperature Sensitivity, Ming Zhu

UNLV Theses, Dissertations, Professional Papers, and Capstones

With the rapid development of integrated circuit (IC) design and manufacturing technology, the transistor size now can be shrunk into only couple of nanometers whereas billions of transistors can be squeezed into a square millimeter, providing unprecedented computation power. However, accompanied with continuous device miniaturization and increased integration density is the explosive growth of on-chip power dissipation and a wide range of temperature fluctuation, which can heavily and negatively affect the delay performance of the circuit, or in the worst case, the circuit may malfunction and the system can be unreliable. Therefore, improved performance resilience against temperature variations has become …

Generator Polynomial Formulation For Parallel Counters With Applications, Lee A. Belfore Ii

Electrical & Computer Engineering Faculty Publications

Parallel counters have been studied for several decades as a component in high speed multipliers and multi-operand adder circuits. Using a generator polynomial as a formalism for describing parallel counters in the general case, parallel counter properties can be derived and inferred. Furthermore, the structure and decomposition of the generator polynomial can suggest different implementation strategies. These include simple implementations of (7,3) and (15,4) parallel counters. By grouping factors, the design of a fast (7,3) parallel counter is presented. Finally, the generator polynomial is extended to permit factors of different weights. This extension provides a means for describing the design …

Synthesis Of Reversible Synchronous Counters, Marek Perkowski, Mozammel H.A. Khan

Electrical and Computer Engineering Faculty Publications and Presentations

In this paper, we concentrate on design of synchronous counters directly from reversible gates.

Synthesis Of Quantum Circuits In Linear Nearest Neighbor Model Using Positive Davio Lattices, Marek Perkowski, Martin Lukac, Dipal Shah, Michitaka Kameyama

Electrical and Computer Engineering Faculty Publications and Presentations

We present a logic synthesis method based on lattices that realize quantum arrays in One-Dimensional Ion Trap technology. This means that all gates are built from 2x2 quantum primitives that are located only on neighbor qubits in a onedimensional space (called also vector of qubits or Linear Nearest Neighbor (LNN) architecture). The Logic circuits designed by the proposed method are realized only with 3*3 Toffoli, Feynman and NOT quantum gates and the usage of the commonly used multi-input Toffoli gates is avoided. This realization method of quantum circuits is different from most of reversible circuits synthesis methods from the literature …

Modal Logic And Its Applications, Explained Using Puzzles And Examples, Marek Perkowski

Electrical and Computer Engineering Faculty Publications and Presentations

1.We shall be concerned, at first, with alethicmodal logic, or modal logic tout court. 2.The starting point, once again, is Aristotle, who was the first to study the relationship between modal statements and their validity. 3.However, the great discussion it enjoyed in the Middle Ages. 4.The official birth date of modal logic is 1921, when Clarence Irving Lewis wrote a famous essay on implication.

Synthesis Of Reversible Circuits For Large Reversible Functions, Marek Perkowski, Nouraddin Alhagi, Maher Hawash

Electrical and Computer Engineering Faculty Publications and Presentations

This paper presents a new algorithmMP (multiple pass) to synthesize large reversible binary circuits without ancilla bits. The well-known MMD algorithm for synthesis of reversible circuits requires to store a truth table (or a Reed-Muller - RM transform) as a 2n vector to represent a reversible function of n variables. This representation prohibits synthesis of large functions. However, in MP we do not store such an exponentially growing data structure. The values of minterms are calculated in MP dynamically, one-by-one, from a set of logic equations that specify the reversible circuit to be designed. This allows for synthesis of large …

Fault Testing Quantum Switching Circuits, Marek Perkowski, Jacob Biamonte

Electrical and Computer Engineering Faculty Publications and Presentations

Test pattern generation is an electronic design automation tool that attempts to find an input (or test) sequence that, when applied to a digital circuit, enables one to distinguish between the correct circuit behavior and the faulty behavior caused by particular faults. The effectiveness of this classical method is measured by the fault coverage achieved for the fault model and the number of generated vectors, which should be directly proportional to test application time. This work address the quantum process validation problem by considering the quantum mechanical adaptation of test pattern generation methods used to test classical circuits. We found …

Inductive Learning Of Quantum Behaviors, Marek Perkowski, Martin Lukac

Electrical and Computer Engineering Faculty Publications and Presentations

In this paper studied are new concepts of robotic behaviors - deterministic and quantum probabilistic. In contrast to classical circuits, the quantum circuit can realize both of these behaviors. When applied to a robot, a quantum circuit controller realizes what we call quantum robot behaviors. We use automated methods to synthesize quantum behaviors (circuits) from the examples (examples are cares of the quantum truth table). The don’t knows (minterms not given as examples) are then converted not only to deterministic cares as in the classical learning, but also to output values generated with various probabilities. The Occam Razor principle, fundamental …

A Transformation Based Algorithm For Ternary Reversible Logic Synthesis Using Universally Controlled Ternary Gates, Marek Perkowski, Eric Curtis

Electrical and Computer Engineering Faculty Publications and Presentations

In this paper a synthesis algorithm for reversible ternary logic cascades is presented. The algorithm can find a solution for any reversible ternary function with n inputs and n outputs utilizing ternary inverter gates and the new (quantum realizable) UCTG gates which are a powerful generalization of ternary Toffoli gates and Generalized Ternary Gates [4]. The algorithm is an extension of the algorithm presented by Dueck, Maslov, and Miller in [3]. A unique feature of this algorithm is that it utilizes no extra wires to generate the outputs. A basic compaction algorithm is defined to improve the results of the …

Multi-Output Esop Synthesis With Cascades Of New Reversible Gate Family, Mozammel H.A. Khan, Marek Perkowski

Electrical and Computer Engineering Faculty Publications and Presentations

A reversible gate maps each output vector into a unique input vector and vice versa. The importance of reversible logic lies in the technological necessity that most "near-future" and all long-term future technologies will have to use reversible gates in order to reduce power. In this paper, a new generalized k*k reversible gate family is proposed. A synthesis method for multi-output (factorized) ESOP using cascades of the new gate family is presented. For utilizing the benefit of product sharing among the ESOPs, two graph-based data structures -connectivity tree and implementation graph are used. Experimental results with some MCNC benchmark functions …

Generalized Inclusive Forms — New Canonical Reed-Muller Forms Including Minimum Esops, Marek Perkowski, Alan Mishchenko, Malgorzata Chzanowka-Jeske

Electrical and Computer Engineering Faculty Publications and Presentations

Reed-Muller (AND/EXOR) expansions play an important role in logic synthesis and circuit design by producing economical and highly-testable implementations of Boolean functions [3–6]. The range of Reed-Muller expansions include canonical forms, i.e. expansions that create unique representations of a Boolean function. Several large families of canonical forms: fixed polarity Reed-Muller forms (FPRMs), generalized Reed-Muller forms (GRMs), Kronecker forms (KROs), and pseudo- Kronecker forms (PKROs), referred to as the Green/Sasao hierarchy, have been described [7–9]. (See Fig. 1 for a settheoretic relationship between these families.)

Multiple-Valued Quantum Logic Synthesis, Marek Perkowski, Anas Al-Rabadi, Pawel Kerttopf

Electrical and Computer Engineering Faculty Publications and Presentations

This paper asks the question: is logic synthesis for quantum computers a practical research subject?

We would like to assume that any two quantum wires can interact, but we are limited by the realization constraints. Structure of atomic bonds in the molecule determines neighborhoods in the circuit. This is similar to restricted routing in FPGA layout - link between logic and layout synthesis known from CMOS design now appears in quantum. Below we are interested only in the so-called “permutation circuits” - their unitary quantum matrices are permutation matrices.

Term Trees In Application To An Effective And Efficient Atpg For And–Exor And And–Or Circuits, Lech Jozwiak, Aleksander Ślusarczyk, Marek Perkowski

Electrical and Computer Engineering Faculty Publications and Presentations

A compact data representation, in which the typically required operations are performed rapidly, and effective and efficient algorithms that work on these representations are the essential elements of a successful CAD tool. The objective of this paper is to present a new data representation—term trees (TTs)—and to discuss its application for an effective and efficient structural automatic test-pattern generation (ATPG). Term trees are decision diagrams similar to BDDs that are particularly suitable for structure representation of AND–OR and AND–EXOR circuits. In the paper, a flexible algorithm for minimum term-tree construction is discussed and an effective and efficient algorithm for ATPG …

Logic Synthesis For A Regular Layout, Marek Perkowski, Yang Xu, Malgorzata Chrzanowska-Jeske

Electrical and Computer Engineering Faculty Publications and Presentations

New algorithms for generating a regular two-dimensional layout representation for multi-output, incompletely specified Boolean functions, called, Pseudo-Symmetric Binary Decision Diagrams (PSBDDs), are presented. The regular structure of the function representation allows accurate prediction of post-layout areas and delays before the layout is physically generated. It simplifies power estimation on the gate level and allows for more accurate power optimization. The theoretical background of the new diagrams, which are based on ideas from contact networks, and the form of decision diagrams for symmetric functions is discussed. PSBDDs are especially well suited for deep sub-micron technologies where the delay of interconnections limits …

Multi-Level Programmable Arrays For Sub-Micron Technology Based On Symmetries, Marek Perkowski, Malgorzata Chrzanowska-Jeske, Yang Xu

Electrical and Computer Engineering Faculty Publications and Presentations

Regular layout is a fundamental concept in VLSI design which can have application in custom design for submicron technologies, designing new architectures for fine-grain Field Programmable Gate Arrays (FPGAs) and Electrically Programmable logic Devices (EPLDs), and minimization of logic functions for existing FPGAs. PLAs are well known examples of regular layouts. Lattice diagrams are another type of regular layouts that have been recently introduced for layout-driven logic synthesis. In this paper we extend and combine theses two ideas, by introducing the multi-level PLA-like structures, composed from multi-output (pseudo) symmetrical lattice planes and other planes (multi-input, multi-output regular blocks). The main …