Engineering Commons^™

Three-Port Bi-Directional Dc–Dc Converter With Solar Pv System Fed Bldc Motor Drive Using Fpga, Arun Kumar Udayakumar, Raghavendra Rajan Vijaya Raghavan, Mohamad Abou Houran, Rajvikram Madurai Elavarasan, Anushkannan Nedumaran Kalavathy, Eklas Hossain

Electrical and Computer Engineering Faculty Publications and Presentations

The increased need for renewable energy systems to generate power, store energy, and connect energy storage devices with applications has become a major challenge. Energy storage using batteries is most appropriate for energy sources like solar, wind, etc. A non-isolated three-port DC–DC-converter energy conversion unit is implemented feeding the brushless DCmotor drive. In this paper, a non-isolated three-port converter is designed and simulated for battery energy storage, interfaced with an output drive. Based on the requirements, the power extracted from the solar panel during the daytime is used to charge the batteries through the three-port converter. The proposed three-port converter …

Implementation And Characterization Of Ahr On A Xilinx Fpga, Andrew J. Dittrich

Theses and Dissertations

A new version of the Adaptive-Hybrid Redundancy (AHR) architecture was developed to be implemented and tested in hardware using Commercial-Off-The-Shelf (COTS) Field-Programmable Gate Arrays (FPGAs). The AHR architecture was developed to mitigate the effects that the Single Event Upset (SEU) and Single Event Transient (SET) radiation effects have on processors and was tested on a Microprocessor without Interlocked Pipeline Stages (MIPS) architecture. The AHR MIPS architecture was implemented in hardware using two Xilinx FPGAs. A Universal Asynchronous Receiver Transmitter (UART) based serial communication network was added to the AHR MIPS design to enable inter-board communication between the two FPGAs. The …

A Primer On Software Defined Radios, Dimitrie C. Popescu, Rolland Vida

Electrical & Computer Engineering Faculty Publications

The commercial success of cellular phone systems during the late 1980s and early 1990 years heralded the wireless revolution that became apparent at the turn of the 21st century and has led the modern society to a highly interconnected world where ubiquitous connectivity and mobility are enabled by powerful wireless terminals. Software defined radio (SDR) technology has played a major role in accelerating the pace at which wireless capabilities have advanced, in particular over the past 15 years, and SDRs are now at the core of modern wireless communication systems. In this paper we give an overview of SDRs that …

Characterizing Security Monitor And Embedded System Performance Across Distinct Risc-V Ip-Cores, Justin C. Tullos

Theses and Dissertations

Embedded systems have seen a rapid integration into all forms of industry as they continue to shrink in size and cost. The increased demand has highlighted a need for secure systems that are robust to attacks and demonstrate reliable performance, especially if the system operation is time-critical. E orts to characterize the performance of secure systems have been obstructed either by proprietary restrictions or ineffective analysis. Proprietary technology limits a comprehensive validation of a system's security and the implications it might have on performance. Performance analysis that is disclosed often lacks sufficient statistical rigor needed for a complex system. A …

A Circle Hough Transform Implementation Using High-Level Synthesis, Carlos Lemus

UNLV Theses, Dissertations, Professional Papers, and Capstones

Circle Hough Transform (CHT) has found applications in biometrics, robotics, and imageanalysis. In this work, the focus is the development of a Field Programmable Gate Array (FPGA) based accelerator that performs a series of procedures and results in circle detection. The design is performed using Vivado High-Level Synthesis (HLS) tools and targeted for a Zynq UltraScale+ ZCU106. The implementation includes the following procedures: Gaussian filter, Sobel edge operator, thresholding, and finally the CHT algorithm. The performance is evaluated based on the execution time as compared to the software (Python code) execution and the analysis tools provided by Vivado HLS tool. …

Investigating Single Precision Floating General Matrix Multiply In Heterogeneous Hardware, Steven Harris

McKelvey School of Engineering Theses & Dissertations

The fundamental operation of matrix multiplication is ubiquitous across a myriad of disciplines. Yet, the identification of new optimizations for matrix multiplication remains relevant for emerging hardware architectures and heterogeneous systems. Frameworks such as OpenCL enable computation orchestration on existing systems, and its availability using the Intel High Level Synthesis compiler allows users to architect new designs for reconfigurable hardware using C/C++. Using the HARPv2 as a vehicle for exploration, we investigate the utility of several of the most notable matrix multiplication optimizations to better understand the performance portability of OpenCL and the implications for such optimizations on this and …

Adaptive-Hybrid Redundancy With Error Injection, Nicholas S. Hamilton, Scott R. Graham, Timothy Carbino, James C. Petrosky, J. Addison Betances

Faculty Publications

Adaptive-Hybrid Redundancy (AHR) shows promise as a method to allow flexibility when selecting between processing speed and energy efficiency while maintaining a level of error mitigation in space radiation environments. Whereas previous work demonstrated AHR’s feasibility in an error free environment, this work analyzes AHR performance in the presence of errors. Errors are deliberately injected into AHR at specific times in the processing chain to demonstrate best and worst case performance impacts. This analysis demonstrates that AHR provides flexibility in processing speed and energy efficiency in the presence of errors

Development And Demonstration Of A Processing And Assembly Pathway For A 3d-Synchronous Field Programmable Gate Array, Robert Carroll

Legacy Theses & Dissertations (2009 - 2024)

Field Programmable Gate Arrays (FPGA) are integrated circuits which can implement virtually any digital function and can be configured by a designer after manufacturing. This is beneficial when dedicated application specific runs are not time or cost effective; however, this flexibility comes at the cost of a substantially higher interconnect overhead. Three-dimensional (3D) integration can offer significant improvements in the FPGA architecture by stacking multiple device layers and interconnecting them in the third or vertical dimension, through the substrate, where path lengths are greatly reduced. This will allow for a higher density of devices and improvements in power consumption, signal …

A Novel Fpga Implementation Of Hierarchical Temporal Memory Spatial Pooler, Paul Jeffrey Mitchell

Boise State University Theses and Dissertations

There is currently a strong focus across the technological landscape to create machines capable of performing complex, objective based tasks in a manner similar to, or superior to a human. Many of the methods being explored in the machine intelligence space require large sets of labeled data to first train, and then classify inputs. Hierarchical Temporal Memory (HTM) is a biologically inspired machine intelligence framework which aims to classify and interpret streaming unlabeled data, without supervision, and be able to detect anomalies in such data.

In software HTM models, increasing the number of “columns” or processing elements to the levels …

A Comparative Analysis Of 1-Level Multiplier-Free Discrete Wavelet Transform Implementations On Fpgas, Husam Alzaq, Burak Berk Üstündağ

Turkish Journal of Electrical Engineering and Computer Sciences

In this article, we investigated the design and implementation aspects of multilevel discrete wavelet transform (DWT) by employing a finite impulse response filter on field programmable gate array platform. We presented two key multiplication-free architectures, namely, the distributed arithmetic algorithm (DAA) and residue number system (RNS). Our goal is to estimate the performance requirements and hardware resources for each approach, allowing for selection of the proper algorithm and implementation of multilevel DAA- and RNS-based DWT. The design has been implemented and synthesized in Xilinx Virtex 6 ML605, taking advantage of Virtex 6?s embedded block RAMs. The results reveal that the …

Fpga-Based Soc For Hardware Implementation Of A Local Histogram-Based Video Shot Detector, Abdessalem Ben Abdelali, Mohamed Nidhal Krifa, Abdellatif Mtibaa

Turkish Journal of Electrical Engineering and Computer Sciences

In this paper, we present a video application example and its implementation in a reconfigurable system-on-chip (SOC) platform. The proposed platform employs the benefits of field programmable gate array (FPGA) technology. A prototype based on a Xilinx Virtex-5 FPGA is developed. The application includes a video shot boundary detection module based on the local histogram (LH) technique. Diverse hardware module versions corresponding to different quantization levels and architectural solutions for an LH-based shot detection system are presented. The developed modules have different hardware resource occupations and can be used in a dynamic way to allow flexible management of the target …

Design And Test Of A New Development Fpga Board For Mobile Robot Research, Baligh Naji, Chokri Abdelmoula, Karim Abbes, Mohamed Masmoudi

Turkish Journal of Electrical Engineering and Computer Sciences

This paper presents the design and testing of a newly developed field programmable gate array (FPGA) board for mobile robot research. The idea consists of interfacing the FPGA to a 16-bit digital signal controller (dsPIC). This idea enables the FPGA designs to communicate with the dsPIC through the integration of per-written driver modules to be used in a wide variety of digital and analog peripheral modules. It also allows the use of a high-performance digital signal processing core in many signal processing-based mobile robot applications. The proposed FPGA board allows users to develop, test, and deploy quick and cost-effective complete …

Design And Implementation Of A Genetic Algorithm Ip Core On An Fpga For Path Planning Of Mobile Robots, Adem Tuncer, Mehmet Yildirim

Turkish Journal of Electrical Engineering and Computer Sciences

This paper presents a hardware realization of a genetic algorithm (GA) for the path planning problem of mobile robots on a field programmable gate array (FPGA). A customized GA intellectual property (IP) core was designed and implemented on an FPGA. A Xilinx xupv5-lx110t FPGA device was used as the hardware platform. The proposed GA IP core was applied to a Pioneer 3-DX mobile robot to confirm its path planning performance. For localization tasks, a camera mounted on the ceiling of the laboratory was utilized to receive images and allow the robot to determine its own location and the obstacles in …

Design And Realization Of A Hybrid Intelligent Controller For A Twin Rotor Mimo System, Jih-Gau Juang, Kai-Ti Tu

Journal of Marine Science and Technology

An intelligent control scheme using a fuzzy switching mechanism, grey prediction and genetic algorithm (GA) is applied to a coupled nonlinear system, called a twin rotor multi-input multi-output system (TRMS). In real-time control, a Xilinx Spartan II SP200 FPGA (Field Programmable Gate Array) is employed to construct a hardware-in-the-loop system through writing VHDL on this FPGA. The objective is to stabilize the TRMS in significant cross-coupled conditions, and to experiment with setpoint control and trajectory tracking. The proposed scheme improves the performance of the PID controller. Control gains and parameters of the fuzzy switching mechanism are obtained by GA. Simulation …

Wave-Based Modeling, Highlighting Underground Sensing And Imaging, Carey Rappaport, Sara Wadia-Fascetti, Miriam Leeser

Sara J. Wadia-Fascetti

No abstract provided.

Wave-Based Modeling, Highlighting Underground Sensing And Imaging, Carey Rappaport, Sara Wadia-Fascetti, Miriam Leeser

Carey Rappaport

No abstract provided.

Wave-Based Modeling, Highlighting Underground Sensing And Imaging, Carey Rappaport, Sara Wadia-Fascetti, Miriam Leeser

Miriam Leeser

No abstract provided.

A Fpga/Dsp Design For Real-Time Fracture Detection Using Low Transient Pulse, Akash Mathur

Theses

This work presents the hardware and software architecture for the detection of fractures and edges in materials. While the detection method is based on the novel concept of Low Transient Pulse (LTP), the overall system implementation is based on two digital microelectronics technologies widely used for signal processing: Digital Signal Processor (DSP) and Field Programmable Gate Array (FPGA). Under the proposed architecture, the DSP carries out the analysis of the received baseband signal at a lower rate and hence can be used for large number of signal channels. The FPGA's master clock runs at a higher frequency (62.5MHz) for the …