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Articles 1 - 17 of 17
Full-Text Articles in Engineering
Efficient Machine Learning: Models And Accelerations, Zhe Li
Efficient Machine Learning: Models And Accelerations, Zhe Li
Dissertations - ALL
One of the key enablers of the recent unprecedented success of machine learning is the adoption of very large models. Modern machine learning models typically consist of multiple cascaded layers such as deep neural networks, and at least millions to hundreds of millions of parameters (i.e., weights) for the entire model. The larger-scale model tend to enable the extraction of more complex high-level features, and therefore, lead to a significant improvement of the overall accuracy. On the other side, the layered deep structure and large model sizes also demand to increase computational capability and memory requirements. In order to achieve …
Acoustic Source Localization With A Vtol Suav Deployable Module, Kory Olney
Acoustic Source Localization With A Vtol Suav Deployable Module, Kory Olney
USF Tampa Graduate Theses and Dissertations
A real time acoustic direction-finding module has been developed to estimate the ele- vation and azimuth of an impulsive event while function aboard a small unmanned air- craft vehicle. The generalized cross-correlation with phase transform method was used to estimate time differences of arrival in an 8 channel microphone array. A linear least squares approach was used to calculate an estimate for the direction of arrival. In order to accomplish this task, a vertical takeoff and landing small unmanned aircraft system was assembled to host the direction finding module. The module itself is made up of an eight-channel synchronous analog-to-digital …
Fpga Multi-Core Processors Power Consumption: Soft- Core Vs. Hard-Core, Marsida Ibro, Gerti Kallbaqi
Fpga Multi-Core Processors Power Consumption: Soft- Core Vs. Hard-Core, Marsida Ibro, Gerti Kallbaqi
UBT International Conference
Actually multi-core processors designs are limited in power consumption and performance. Consequently, it is not possible to optimize further the performance without increasing power consumption. The main challenge in multi-core processors is the fact that they have heterogeneous hardware components. This article will study different technologies for implementing multi-core processors in FPGA devices. The minimum requirement to ensure low power consumption is parallelism. The purpose of this study is to highlight the latest methodologies used in terms of environment, clock signal, testing, flexibility, cost, availability and power consumption.
On-Chip Communication And Security In Fpgas, Shivukumar Basanagouda Patil
On-Chip Communication And Security In Fpgas, Shivukumar Basanagouda Patil
Masters Theses
Innovations in Field Programmable Gate Array (FPGA) manufacturing processes and architectural design have led to the development of extremely large FPGAs. There has also been a widespread adaptation of these large FPGAs in cloud infrastructures and data centers to accelerate search and machine learning applications. Two important topics related to FPGAs are addressed in this work: on-chip communication and security. On-chip communication is quickly becoming a bottleneck in to- day’s large multi-million gate FPGAs. Hard Networks-on-Chip (NoC), made of fixed silicon, have been shown to provide low power, high speed, flexible on-chip communication. An iterative algorithm for routing pre-scheduled time-division-multiplexed …
Compact Hardware Implementation Of A Sha-3 Core For Wireless Body Sensor Networks, Yi Yang, Debiao He, Neeraj Kumar, Sherali Zeadally
Compact Hardware Implementation Of A Sha-3 Core For Wireless Body Sensor Networks, Yi Yang, Debiao He, Neeraj Kumar, Sherali Zeadally
Information Science Faculty Publications
One of the most important Internet of Things applications is the wireless body sensor network (WBSN), which can provide universal health care, disease prevention, and control. Due to large deployments of small scale smart sensors in WBSNs, security, and privacy guarantees (e.g., security and safety-critical data, sensitive private information) are becoming a challenging issue because these sensor nodes communicate using an open channel, i.e., Internet. We implement data integrity (to resist against malicious tampering) using the secure hash algorithm 3 (SHA-3) when smart sensors in WBSNs communicate with each other using the Internet. Due to the limited resources (i.e., storage, …
A Basic, Four Logic Cluster, Disjoint Switch Connected Fpga Architecture, Joseph Prachar
A Basic, Four Logic Cluster, Disjoint Switch Connected Fpga Architecture, Joseph Prachar
Computer Engineering
This paper seeks to describe the process of developing a new FPGA architecture from nothing, both in terms of knowledge about FPGAs and in initial design material. Specifically, this project set out to design an FPGA architecture which can implement a simple state machine type design with 10 inputs, 10 outputs and 10 states. The open source Verilog-to-Routing FPGA CAD flow tool was used in order to synthesize, place, and route HDL files onto the architecture. This project was completed in terms of the spirit of the original goals of implementing an FPGA from scratch. Although, the project resulted in …
Efficient Fpga Soc Processing Design For A Small Uav Radar, Luke Oliver Newmeyer
Efficient Fpga Soc Processing Design For A Small Uav Radar, Luke Oliver Newmeyer
Theses and Dissertations
Modern radar technology relies heavily on digital signal processing. As radar technology pushes the boundaries of miniaturization, computational systems must be developed to support the processing demand. One particular application for small radar technology is in modern drone systems. Many drone applications are currently inhibited by safety concerns of autonomous vehicles navigating shared airspace. Research in radar based Detect and Avoid (DAA) attempts to address these concerns by using radar to detect nearby aircraft and choosing an alternative flight path. Implementation of radar on small Unmanned Air Vehicles (UAV), however, requires a lightweight and power efficient design. Likewise, the radar …
Efficient Fpga Soc Processing Design For A Small Uav Radar, Luke Oliver Newmeyer
Efficient Fpga Soc Processing Design For A Small Uav Radar, Luke Oliver Newmeyer
Theses and Dissertations
Modern radar technology relies heavily on digital signal processing. As radar technology pushes the boundaries of miniaturization, computational systems must be developed to support the processing demand. One particular application for small radar technology is in modern drone systems. Many drone applications are currently inhibited by safety concerns of autonomous vehicles navigating shared airspace. Research in radar based Detect and Avoid (DAA) attempts to address these concerns by using radar to detect nearby aircraft and choosing an alternative flight path. Implementation of radar on small Unmanned Air Vehicles (UAV), however, requires a lightweight and power efficient design. Likewise, the radar …
Progressive Network Deployment, Performance, And Control With Software-Defined Networking, Daniel J. Casey
Progressive Network Deployment, Performance, And Control With Software-Defined Networking, Daniel J. Casey
Theses and Dissertations
The inflexible nature of traditional computer networks has led to tightly-integrated systems that are inherently difficult to manage and secure. New designs move low-level network control into software creating software-defined networks (SDN). Augmenting an existing network with these enhancements can be expensive and complex. This research investigates solutions to these problems. It is hypothesized that an add-on device, or "shim" could be used to make a traditional switch behave as an OpenFlow SDN switch while maintaining reasonable performance. A design prototype is found to cause approximately 1.5% reduction in throughput for one ow and less than double increase in latency, …
Towards Tools For Achieving Third-Party Ip Assurance, Sean Talbot Jensen
Towards Tools For Achieving Third-Party Ip Assurance, Sean Talbot Jensen
Theses and Dissertations
Intellectual Property (IP) is used to speed up the design process and save money. The use of IP and complex CAD tools reduce visibility into the design and what is actually happening during synthesis and implementation. All of the complexity makes it easier for an attacker to insert malicious logic or tamper with the design in ways that are difficult to detect. Not very much work has been done towards the creation of tools to facilitate the safe use of 3rd-party IP. This work presents Physical and Functional Assurance, two approaches that aim to accomplish this task through physically and …
A Flexible Fpga-Assisted Framework For Remote Attestation Of Internet Connected Embedded Devices, Jared Russell Patten
A Flexible Fpga-Assisted Framework For Remote Attestation Of Internet Connected Embedded Devices, Jared Russell Patten
Theses and Dissertations
Embedded devices permeate our every day lives. They exist in our vehicles, traffic lights, medical equipment, and infrastructure controls. In many cases, improper functionality of these devices can present a physical danger to their users, data or financial loss, etc. Improper functionality can be a result of software or hardware bugs, but now more than ever, is often the result of malicious compromise and tampering, or as it is known colloquially "hacking". We are beginning to witness a proliferation of cyber-crime, and as more devices are built with internet connectivity (in the so called "Internet of Things"), security should be …
Efficient Implementation Of Ieee 802.11i Wi-Fi Security (Wpa2-Psk) Standard Using Fpga, Atal Bajracharya
Efficient Implementation Of Ieee 802.11i Wi-Fi Security (Wpa2-Psk) Standard Using Fpga, Atal Bajracharya
Masters Theses
The rationale behind the thesis was to design efficient implementations of cryptography algorithms used for Wi-Fi Security as per IEEE 802.11i Wi-Fi Security (WPA2-PSK) standard. The focus was on software implementation of Password-Based Key Derivation Function 2 (PBKDF2) using Keyed-Hash Message Authentication Code (HMAC)-SHA1, which is used for authentication, and, hardware implementation of AES-256 cipher, which is used for data confidentiality.
In this thesis, PBKDF2 based on HMAC-SHA1 was implemented on software using C programming language, and, AES-256 was implemented on hardware using Verilog HDL. The overall implementation was designed and tested on Nexys4 FPGA board. The performance of the …
Highly Accurate And Sensitive Short Read Aligner, Mehmet Yağmur Gök, Sezer Gören Uğurdağ, Cem Ünsalan, Mahmut Şami̇l Sağiroğlu
Highly Accurate And Sensitive Short Read Aligner, Mehmet Yağmur Gök, Sezer Gören Uğurdağ, Cem Ünsalan, Mahmut Şami̇l Sağiroğlu
Turkish Journal of Electrical Engineering and Computer Sciences
Next-generation sequencing generates large numbers of short reads from DNA. This makes it difficult to process and store. Therefore, efficient sequence alignment and mapping techniques are needed in bioinformatics. Alignment and mapping are the basic steps involved in genetic data analysis. The Smith-Waterman (SW) algorithm, a well-known dynamic programming algorithm, is often used for this purpose. In this work, we propose to utilize Phred quality scores in Gotoh's affine gap model to increase the accuracy and sensitivity of the SW algorithm. Hardware platforms such as FPGAs and GPUs are commonly used to solve computationally expensive problems. In this work, a …
Fpga-Based On-Board Geometric Calibration For Linear Ccd Array Sensors, Guoqing Zhou, Linjun Jiang, Jingjin Huang, Rongting Zhang, Dequan Liu, Xiang Zhou, Oktay Baysal
Fpga-Based On-Board Geometric Calibration For Linear Ccd Array Sensors, Guoqing Zhou, Linjun Jiang, Jingjin Huang, Rongting Zhang, Dequan Liu, Xiang Zhou, Oktay Baysal
Mechanical & Aerospace Engineering Faculty Publications
With increasing demands in real-time or near real-time remotely sensed imagery applications in such as military deployments, quick response to terrorist attacks and disaster rescue, the on-board geometric calibration problem has attracted the attention of many scientists in recent years. This paper presents an on-board geometric calibration method for linear CCD sensor arrays using FPGA chips. The proposed method mainly consists of four modules—Input Data, Coefficient Calculation, Adjustment Computation and Comparison—in which the parallel computations for building the observation equations and least squares adjustment, are implemented using FPGA chips, for which a decomposed matrix inversion method is presented. A Xilinx …
Analysis Of High Performance Scientific Programming Workflows, Withana Kankanamalage Umayanganie Klaassen
Analysis Of High Performance Scientific Programming Workflows, Withana Kankanamalage Umayanganie Klaassen
Open Access Theses & Dissertations
Substantial time is spent on building, optimizing and maintaining large-scale software that is run on supercomputers. However, little has been done to utilize overall resources efficiently when it comes to including expensive human resources. The community is beginning to acknowledge that optimizing the hardware performance such as speed and memory bottlenecks contributes less to the overall productivity than does the development lifecycle of high-performance scientific applications. Researchers are beginning to look at overall scientific workflows for high performance computing. Scientific programming productivity is measured by time and effort required to develop, configure, and maintain a simulation experiment and its constituent …
A Proposed Approach To Hybrid Software-Hardware Application Design For Enhanced Application Performance, Alex Shipman
A Proposed Approach To Hybrid Software-Hardware Application Design For Enhanced Application Performance, Alex Shipman
Graduate Theses and Dissertations
One important aspect of many commercial computer systems is their performance; therefore, system designers seek to improve the performance next-generation systems with respect to previous generations. This could mean improved computational performance, reduced power consumption leading to better battery life in mobile devices, smaller form factors, or improvements in many areas. In terms of increased system speed and computation performance, processor manufacturers have been able to increase the clock frequency of processors up to a point, but now it is more common to seek performance gains through increased parallelism (such as a processor having more processor cores on a single …
Fpga-Based Ir Localization Sensor, Samuel I. Susanto
Fpga-Based Ir Localization Sensor, Samuel I. Susanto
Browse all Theses and Dissertations
Pursuit-evasion scenarios are common in both natural and man-made systems. Often times, the pursuer and evader maneuver in response to each others actions using relative information based on the geometry of the agents and potential obstacles within the environment. The pursuer needs the target's bearing angle in order to plan a trajectory or path to capture it. We propose an FPGA-based infrared sensor array to detect up to 6 agents' bearing angles simultaneously. The final output of the sensor is the bearing angle of other agents. The sensor was tested and validated experimentally. Implementing the sensor and transmitter pair on …