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Architecture

Electrical and Computer Engineering Faculty Research & Creative Works

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Full-Text Articles in Engineering

Defect-Tolerant Gate Macro Mapping & Placement In Clock-Free Nanowire Crossbar Architecture, Ravi Bonam, Yong-Bin Kim, Minsu Choi Sep 2007

Defect-Tolerant Gate Macro Mapping & Placement In Clock-Free Nanowire Crossbar Architecture, Ravi Bonam, Yong-Bin Kim, Minsu Choi

Electrical and Computer Engineering Faculty Research & Creative Works

Recently, we proposed a new clock-free nanowire crossbar architecture based on a delayinsensitive paradigm called Null Convention Logic (NCL). The proposed architecture has simple periodic structure that is suitable for non-deterministic nanoscale assembly and does not require a clock distribution network - so it is intrinsically free from timing-related failure modes. Even though the proposed architecture offers improved manufacturability, it is still not free from defects. This paper elaborates on the different programming techniques to map a given threshold gate macro on a random PGMB (Programmable Gate Macro Block) with predefined dimension. Defect-Aware and Defect Unaware approaches have been considered …


Clock-Free Nanowire Crossbar Architecture Based On Null Convention Logic (Ncl), Ravi Bonam, Shikha Chaudhary, Yadunandana Yellambalase, Minsu Choi Aug 2007

Clock-Free Nanowire Crossbar Architecture Based On Null Convention Logic (Ncl), Ravi Bonam, Shikha Chaudhary, Yadunandana Yellambalase, Minsu Choi

Electrical and Computer Engineering Faculty Research & Creative Works

There have been numerous nanowire crossbar architectures proposed till date, although all of them are envisioned to be synchronous (i.e., clocked). The clock is an important part in a circuit and it needs to be connected to all the components to synchronize their operation. Considering non-deterministic nature of nanoscale integration, realizing them on a nano wire crossbar system would be quite cumbersome. Unlike the conventional clocked counterparts, a new clock-free crossbar architecture is proposed to resolve the issues with clocked counterparts in this paper, where the use of clock is eliminated from the architecture. This has been done by implementing …