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Applied sciences

VLSI and Circuits, Embedded and Hardware Systems

2012

Articles 1 - 12 of 12

Full-Text Articles in Engineering

A Silicon Carbide Based Solid-State Fault Current Limiter For Modern Power Distribution Systems, Erik Darnell Johnson Dec 2012

A Silicon Carbide Based Solid-State Fault Current Limiter For Modern Power Distribution Systems, Erik Darnell Johnson

Graduate Theses and Dissertations

The fault current limiter represents a developing technology which will greatly improve the reliability and stability of the power grid. By reducing the magnitude of fault currents in distribution systems, fault current limiters can alleviate much of the damage imposed by these events. Solid-state fault current limiters in particular offer many improved capabilities in comparison to the power system protection equipment which is currently being used for fault current mitigation. The use of silicon carbide power semiconductor devices in solid-state fault current limiters produces a system that would help to advance the infrastructure of the electric grid.

A solid-state fault …


Study Of Current Optocoupler Techniques And Applications For Isolation Of Sensing And Control Signals In Dc-Dc Converters, Jake Williams Dec 2012

Study Of Current Optocoupler Techniques And Applications For Isolation Of Sensing And Control Signals In Dc-Dc Converters, Jake Williams

Graduate Theses and Dissertations

There is a need for power switches that can operate at high voltage, high temperature, and high switching frequencies with low losses. Power switches fabricated from wide bandgap materials such as silicon carbide (SiC) or gallium nitride (GaN) can outperform conventional silicon switches due to material property advantages. Another common problem in grid-connected applications is the need for high voltage-isolation of gate drivers and control circuitry while operating efficiently at the high switching frequencies, high power density, and high temperatures made possible by wide bandgap devices. Transformers cannot operate at the temperatures of these wide bandgap devices and a new …


Design And Analysis Of An Adaptive Asynchronous System Architecture For Energy Efficiency, Brent Michael Hollosi Dec 2012

Design And Analysis Of An Adaptive Asynchronous System Architecture For Energy Efficiency, Brent Michael Hollosi

Graduate Theses and Dissertations

Power has become a critical design parameter for digital CMOS integrated circuits. With performance still garnering much concern, a central idea has emerged: minimizing power consumption while maintaining performance. The use of dynamic voltage scaling (DVS) with parallelism has shown to be an effective way of saving power while maintaining performance. However, the potency of DVS and parallelism in traditional, clocked synchronous systems is limited because of the strict timing requirements such systems must comply with. Delay-insensitive (DI) asynchronous systems have the potential to benefit more from these techniques due to their flexible timing requirements and high modularity. This dissertation …


The Development And Packaging Of A High-Density, Three-Phase, Silicon Carbide (Sic) Motor Drive, Jared Hornberger Dec 2012

The Development And Packaging Of A High-Density, Three-Phase, Silicon Carbide (Sic) Motor Drive, Jared Hornberger

Graduate Theses and Dissertations

Technology advances within the power electronics field are resulting in systems characterized by higher operating efficiencies, reduced footprint, minimal form factor, and decreasing mass. In particular, these attributes and characteristics are being inserted into numerous consumer applications, such as light-emitting diode lighting, compact fluorescent lighting, smart phones, and tablet PCs, to industrial applications that include hybrid, electric, and plug-in electric vehicles and more electric aircraft. To achieve the increase in energy efficiency and significant reduction in size and mass of these systems, power semiconductor device manufacturers are developing silicon carbide (SiC) semiconductor technology.

In this dissertation, the author discusses the …


Delay Insensitive Ternary Logic Utilizing Cmos And Cntfet, Ravi Sankar Parameswaran Nair Aug 2012

Delay Insensitive Ternary Logic Utilizing Cmos And Cntfet, Ravi Sankar Parameswaran Nair

Graduate Theses and Dissertations

As digital circuit design continues to evolve due to progress of semiconductor processes well into the sub 100nm range, clocked architectures face limitations in a number of cases where clockless asynchronous architectures require substantially less power, generate less noise, and produce less electromagnetic interference (EMI). This dissertation develops the Delay Insensitive Ternary Logic (DITL) asynchronous design paradigm that combines the designs aspects of similar Dual-Rail asynchronous paradigms and Boolean logic to create a single wire per bit, three voltage signaling and logic scheme.

DITL is designed at the transistor level using multi-threshold CMOS and carbon nanotube (CNT) FETs to develop …


Flexible Circuits For Aerospace Applications With Special Emphasis On Rf Connectors, Abhishek Nareshraj Singh Aug 2012

Flexible Circuits For Aerospace Applications With Special Emphasis On Rf Connectors, Abhishek Nareshraj Singh

Graduate Theses and Dissertations

The current work focused on the study of flexible electronic circuits for use in aerospace applications with emphasis on RF Connectors. The electrical and mechanical performance of the flexible circuits was studied and compared to a standard coaxial cable for feasibility study in avionics space. Also, Anisotropic Conductive Films (ACF) are studied for connecting the flexible RF connectors and their performance studied for electrical and mechanical behavior with change in bonding parameters.


Comparison Of Various Pipelined And Non-Pipelined Scl 8051 Alus, Jingyi Zhao Aug 2012

Comparison Of Various Pipelined And Non-Pipelined Scl 8051 Alus, Jingyi Zhao

Graduate Theses and Dissertations

This paper describes the development of an 8-bit SCL 8051 ALU with two versions: SCL 8051 ALU with nsleep and sleep signals and SCL 8051 ALU without nsleep. Both versions have combinational logic (C/L), registers, and completion components, which all utilize slept gates. Both three-stage pipelined and non-pipelined designs were examined for both versions. The four designs were compared in terms of area, speed, leakage power, average power and energy per operation. The SCL 8051 ALU without nsleep is smaller and faster, but it has greater leakage power. It also has lower average power, and less energy consumption than …


Ultra-Low Voltage Digital Circuits And Extreme Temperature Electronics Design, Aaron J. Arthurs Aug 2012

Ultra-Low Voltage Digital Circuits And Extreme Temperature Electronics Design, Aaron J. Arthurs

Graduate Theses and Dissertations

Certain applications require digital electronics to operate under extreme conditions e.g., large swings in ambient temperature, very low supply voltage, high radiation. Such applications include sensor networks, wearable electronics, unmanned aerial vehicles, spacecraft, and energyharvesting systems. This dissertation splits into two projects that study digital electronics supplied by ultra-low voltages and build an electronic system for extreme temperatures. The first project introduces techniques that improve circuit reliability at deep subthreshold voltages as well as determine the minimum required supply voltage. These techniques address digital electronic design at several levels: the physical process, gate design, and system architecture. This dissertation analyzes …


Silicon Germanium Sram And Rom Designs For Wide Temperature Range Space Applications, Matthew Barlow May 2012

Silicon Germanium Sram And Rom Designs For Wide Temperature Range Space Applications, Matthew Barlow

Graduate Theses and Dissertations

This thesis presents a design flow from specifications and feature requirements to embeddable blocks of SRAM and ROM designs from 64 bytes to 1 kilobyte that are suitable for lunar environments. The design uses the IBM SiGe 5AM BiCMOS 0.5 micron process for a synchronous memory system capable of operating at a clock frequency of 25 MHz. Radiation mitigation techniques are discussed and implemented to harden the design against total ionizing dose (TID), single-event upset (SEU), and single-event latch-up (SEL). The memory arrays are also designed to operate over the wide temperature range of -180 °C to 125 °C. Design, …


Experimental Study Of Novel Materials And Module For Cryogenic (4k) Superconducting Multi-Chip Modules, Ranjith John May 2012

Experimental Study Of Novel Materials And Module For Cryogenic (4k) Superconducting Multi-Chip Modules, Ranjith John

Graduate Theses and Dissertations

The objectives of this proposal are to understand the science and technology of interfaces in the packaging of superconducting electronic (SCE) multichip modules (MCMs) at 4 K. The thermal management issue of the current SCE-MCMs was examined and the package assembly was optimized. A novel thermally conducting and electrically insulating nano-engineered polymer was developed for the thermal management of SCE-MCMs for 4 K cryogenic packaging. Finally, the nano-engineered polymer was integrated as underfill in a SCE-MCM and the thermal and electrical performance of SCE-MCM was demonstrated at 4 K.

Niobium based superconducting electronics (SCE) are the fastest known digital logic …


Characterization And Modeling Of 4h-Sic Low Voltage Mosfets And Power Mosfets, Mihir Mudholkar May 2012

Characterization And Modeling Of 4h-Sic Low Voltage Mosfets And Power Mosfets, Mihir Mudholkar

Graduate Theses and Dissertations

The integration of low voltage and high voltage circuits on SiC has profound applications. SiC power devices have proved their superiority in terms of high temperature operation, faster switching frequencies and larger power densities when compared with Si power devices. The control of SiC power devices however, lies in the hands of low voltage circuits built on Si. Thus, there exists a separation in the overall system between the low voltage and high voltage side, which increases system cost, weight and reduces efficiency. With the advancement in low voltage SiC processing technology, low voltage control circuits can be made on …


Ultra-Low Power And Radiation Hardened Asynchronous Circuit Design, Liang Zhou May 2012

Ultra-Low Power And Radiation Hardened Asynchronous Circuit Design, Liang Zhou

Graduate Theses and Dissertations

This dissertation proposes an ultra-low power design methodology called bit-wise MTNCL for bit-wise pipelined asynchronous circuits, which combines multi-threshold CMOS (MTCMOS) with bit-wise pipelined NULL Convention Logic (NCL) systems. It provides the leakage power advantages of an all high-Vt implementation with a reasonable speed penalty compared to the all low-Vt implementation, and has negligible area overhead. It was enhanced to handle indeterminate standby states. The original MTNCL concept was enhanced significantly by sleeping Registers and Completion Logic as well as Combinational circuits to reduce area, leakage power, and energy per operation.

This dissertation also develops an architecture that allows NCL …