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VLSI and Circuits, Embedded and Hardware Systems

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Silicon Germanium Bicmos Comparator Designed For Use In An Extreme Environment Analog To Digital Converter, Benjamin Riley Sissons May 2017

Silicon Germanium Bicmos Comparator Designed For Use In An Extreme Environment Analog To Digital Converter, Benjamin Riley Sissons

Graduate Theses and Dissertations

This thesis demonstrates the process of creating a radiation hardened and extreme temperature operating comparator from start to finish in the 90 nm SiGe 9HP process node. This includes the entire design flow from examining comparator topologies, to designing the initial comparator circuits, to simulating the comparator over a temperature range of -196°C to 125°C, and finally the testing of the fabricated circuit. To verify the circuit would work at low temperatures, several new device models were created that could be used for simulations at -196°C. In addition to its properties as a standalone comparator, the circuit was also used …


Short-Circuit Protection For Low-Voltage Dc Distribution Systems Based On Solid-State Circuit Breakers, Sharthak Munasib May 2017

Short-Circuit Protection For Low-Voltage Dc Distribution Systems Based On Solid-State Circuit Breakers, Sharthak Munasib

Graduate Theses and Dissertations

Proper short-circuit protection in dc distribution systems has provided an austere challenge to researchers as the development of commercially-viable equipment providing fast operation, coordination and reliability still continues. The objective of this thesis is to analyze issues associated with short-circuit protection of low-voltage dc (LVDC) distribution systems and propose a short-circuit protection methodology based on solid-state circuit breakers (SSCBs) that provides fault-current limiting (FCL). Simulation results for a simplified notional 1-kVdc distribution system, performed in MATLAB/SIMULINKTM, would be presented to illustrate that SSCB solutions based on reverse-blocking integrated gate-commutated thyristors (RB-IGCT) are feasible for low-voltage dc distribution systems but requires …


Si-Based Germanium-Tin (Gesn) Emitters For Short-Wave Infrared Optoelectronics, Seyed Amir Ghetmiri Dec 2016

Si-Based Germanium-Tin (Gesn) Emitters For Short-Wave Infrared Optoelectronics, Seyed Amir Ghetmiri

Graduate Theses and Dissertations

Conventional integrated electronics have reached a physical limit, and their efficiency has been influenced by the generated heat in the high-density electronic packages. Integrated photonic circuits based on the highly developed Si complementary-metal-oxide-semiconductor (CMOS) infrastructure was proposed as a viable solution; however, Si-based emitters are the most challenging component for the monolithic integrated photonic circuits. The indirect bandgap of silicon and germanium is a bottleneck for the further development of photonic and optoelectronic integrated circuits.

The Ge1-xSnx alloy, a group IV material system compatible with Si CMOS technology, was suggested as a desirable material that theoretically exhibits a direct bandgap …


Compact Modeling Of Sic Insulated Gate Bipolar Transistors, Sonia Perez Aug 2016

Compact Modeling Of Sic Insulated Gate Bipolar Transistors, Sonia Perez

Graduate Theses and Dissertations

This thesis presents a unified (n-channel and p-channel) silicon/silicon carbide Insulated Gate Bipolar Transistor (IGBT) compact model in both MAST and Verilog-A formats. Initially, the existing MAST model mobility equations were updated using recently referenced silicon carbide (SiC) data. The updated MAST model was then verified for each device tested. Specifically, the updated MAST model was verified for the following IGBT devices and operation temperatures: n-channel silicon at 25 ˚C and at 125 ˚C; n-channel SiC at 25 ˚C and at 175 ˚C; and p-channel SiC at 150 ˚C and at 250 ˚C. Verification was performed through capacitance, DC output …


Design And Analysis Of An Asynchronous Microcontroller, Michael Hinds Aug 2016

Design And Analysis Of An Asynchronous Microcontroller, Michael Hinds

Graduate Theses and Dissertations

This dissertation presents the design of the most complex MTNCL circuit to date. A fully functional MTNCL MSP430 microcontroller is designed and benchmarked against an open source synchronous MSP430. The designs are compared in terms of area, active energy, and leakage energy. Techniques to reduce MTNCL pipeline activity and improve MTNCL register file area and power consumption are introduced. The results show the MTNCL design to have superior leakage power characteristics. The area and active energy comparisons highlight the need for better MTNCL logic synthesis techniques.


Asynchronous Data Processing Platforms For Energy Efficiency, Performance, And Scalability, Liang Men Aug 2016

Asynchronous Data Processing Platforms For Energy Efficiency, Performance, And Scalability, Liang Men

Graduate Theses and Dissertations

The global technology revolution is changing the integrated circuit industry from the one driven by performance to the one driven by energy, scalability and more-balanced design goals. Without clock-related issues, asynchronous circuits enable further design tradeoffs and in operation adaptive adjustments for energy efficiency. This dissertation work presents the design methodology of the asynchronous circuit using NULL Convention Logic (NCL) and multi-threshold CMOS techniques for energy efficiency and throughput optimization in digital signal processing circuits. Parallel homogeneous and heterogeneous platforms implementing adaptive dynamic voltage scaling (DVS) based on the observation of system fullness and workload prediction are developed for balanced …


Correcting Current Imbalances In Three-Phase Four-Wire Distribution Systems, Vinson Joseph Jones May 2016

Correcting Current Imbalances In Three-Phase Four-Wire Distribution Systems, Vinson Joseph Jones

Graduate Theses and Dissertations

The objective of this thesis is to present the theory, design, construction, and testing of a proposed solution to unbalanced current loading on three-phase four-wire systems. The Unbalanced Current Static Compensator is the name of the prototype; herein referred to as the UCSC. The purpose of this prototype is to redistribute current between the three phases of a distribution system. Through this redistribution, negative- and zero-sequence currents are eliminated and a balanced system is seen upstream from the point of installation.

The UCSC consists of three separate single-phase H-bridge inverters that all share the same dc-link capacitor. Each of these …


Design Of An Assistive Technology Adaptive Switch Using An Inertial Measurement Unit, Ethan Storm Williams May 2016

Design Of An Assistive Technology Adaptive Switch Using An Inertial Measurement Unit, Ethan Storm Williams

Graduate Theses and Dissertations

A new assistive technology switch for people with disabilities was developed utilizing an Inertial Measurement Unit (IMU) as the sensor technology. The hardware can be customized through firmware to provide custom switch activations on a person by person basis. The firmware is customized to recognize specific data features in the IMU data which identify the desired switch activation movement performed by the user. In this way, the switch can be adapted to activate based on the movements of the user. During this research, the generic hardware platform, including the IMU sensor technology and Bluetooth communications, was designed and tested. An …


A Reconfigurable Digital-To-Analog Converter With Supply Invariant Linearity, Nicholas J. Chiolino Dec 2013

A Reconfigurable Digital-To-Analog Converter With Supply Invariant Linearity, Nicholas J. Chiolino

Graduate Theses and Dissertations

A novel reconfigurable digital-to-analog converter (DAC) with supply independent linearity is presented. The process agnostic converter achieves wide supply range operation and re-configurability by being charge based. This converter consists of a 7-bit parallel digital input control core and an analog "summing" core utilizing charging capacitors with an operational transconductance amplifier in a voltage-follower configuration. This topology is highly configurable to allow for optimization across process voltages, step sizes and low power operation. The specification of the DAC is (1) supply independence (2) low power operation (3) operation up to 200 kHz and (4) conversion control through a DAC enable …


Analysis Of Parameter Tuning On Energy Efficiency In Asynchronous Circuits, Justin Thomas Roark Aug 2013

Analysis Of Parameter Tuning On Energy Efficiency In Asynchronous Circuits, Justin Thomas Roark

Graduate Theses and Dissertations

Power and energy consumption are the primary concern of the digital integrated circuit (IC) industry. Asynchronous logic, in the past several years, has increased in popularity due to its low power nature. This thesis analyzes a collection of array multipliers with different parameters to compare two asynchronous design paradigms, NULL Convention Logic (NCL) and Multi-Threshold NULL Convention Logic (MTNCL). Several commercially available pieces of software and custom scripts are used to analyze the asynchronous circuits and their components to provide the energy consumption estimation on various parts of each circuit. The analysis of the software results revealed that MTNCL circuits …


Cad Tool Design For Ncl And Mtncl Asynchronous Circuits, Vijay Mani Pillai Aug 2013

Cad Tool Design For Ncl And Mtncl Asynchronous Circuits, Vijay Mani Pillai

Graduate Theses and Dissertations

This thesis presents an implementation of a method developed to readily convert Boolean designs into an ultra-low power asynchronous design methodology called MTNCL, which combines multi-threshold CMOS (MTCMOS) with NULL Convention Logic (NCL) systems. MTNCL provides the leakage power advantages of an all high-Vt implementation with a reasonable speed penalty compared to the all low-Vt implementation, and has negligible area overhead. The proposed tool utilizes industry-standard CAD tools. This research also presents an Automated Gate-Level Pipelining with Bit-Wise Completion (AGLPBW) method to maximize throughput of delay-insensitive full-word pipelined NCL circuits. These methods have been integrated into the Mentor Graphics and …


Design, Layout, And Testing Of A Silicon Carbide-Based Under Voltage Lock-Out Circuit, Michael Dalan Glover May 2013

Design, Layout, And Testing Of A Silicon Carbide-Based Under Voltage Lock-Out Circuit, Michael Dalan Glover

Graduate Theses and Dissertations

Silicon carbide-based power devices play an increasingly important role in modern power conversion systems. Finding a means to reduce the size and complexity of these systems by even incremental amounts can have a significant impact on cost and reliability. One approach to achieving this goal is the die-level integration of gate driver circuitry with the SiC power devices. Aside from cost reductions, there are significant advantages to the integration of the gate driver circuits with the power devices. By integrating the gate driver circuitry with the power devices, the parasitic inductances traditionally seen between the gate driver and the switching …


Cad Tools For Synthesis Of Sleep Convention Logic, Parviz Palangpour May 2013

Cad Tools For Synthesis Of Sleep Convention Logic, Parviz Palangpour

Graduate Theses and Dissertations

This dissertation proposes an automated flow for the Sleep Convention Logic (SCL) asynchronous design style. The proposed flow synthesizes synchronous RTL into an SCL netlist. The flow utilizes commercial design tools, while supplementing missing functionality using custom tools. A method for determining the performance bottleneck in an SCL design is proposed. A constraint-driven method to increase the performance of linear SCL pipelines is proposed. Several enhancements to SCL are proposed, including techniques to reduce the number of registers and total sleep capacitance in an SCL design.


A Silicon Carbide Based Solid-State Fault Current Limiter For Modern Power Distribution Systems, Erik Darnell Johnson Dec 2012

A Silicon Carbide Based Solid-State Fault Current Limiter For Modern Power Distribution Systems, Erik Darnell Johnson

Graduate Theses and Dissertations

The fault current limiter represents a developing technology which will greatly improve the reliability and stability of the power grid. By reducing the magnitude of fault currents in distribution systems, fault current limiters can alleviate much of the damage imposed by these events. Solid-state fault current limiters in particular offer many improved capabilities in comparison to the power system protection equipment which is currently being used for fault current mitigation. The use of silicon carbide power semiconductor devices in solid-state fault current limiters produces a system that would help to advance the infrastructure of the electric grid.

A solid-state fault …


Study Of Current Optocoupler Techniques And Applications For Isolation Of Sensing And Control Signals In Dc-Dc Converters, Jake Williams Dec 2012

Study Of Current Optocoupler Techniques And Applications For Isolation Of Sensing And Control Signals In Dc-Dc Converters, Jake Williams

Graduate Theses and Dissertations

There is a need for power switches that can operate at high voltage, high temperature, and high switching frequencies with low losses. Power switches fabricated from wide bandgap materials such as silicon carbide (SiC) or gallium nitride (GaN) can outperform conventional silicon switches due to material property advantages. Another common problem in grid-connected applications is the need for high voltage-isolation of gate drivers and control circuitry while operating efficiently at the high switching frequencies, high power density, and high temperatures made possible by wide bandgap devices. Transformers cannot operate at the temperatures of these wide bandgap devices and a new …


Design And Analysis Of An Adaptive Asynchronous System Architecture For Energy Efficiency, Brent Michael Hollosi Dec 2012

Design And Analysis Of An Adaptive Asynchronous System Architecture For Energy Efficiency, Brent Michael Hollosi

Graduate Theses and Dissertations

Power has become a critical design parameter for digital CMOS integrated circuits. With performance still garnering much concern, a central idea has emerged: minimizing power consumption while maintaining performance. The use of dynamic voltage scaling (DVS) with parallelism has shown to be an effective way of saving power while maintaining performance. However, the potency of DVS and parallelism in traditional, clocked synchronous systems is limited because of the strict timing requirements such systems must comply with. Delay-insensitive (DI) asynchronous systems have the potential to benefit more from these techniques due to their flexible timing requirements and high modularity. This dissertation …


The Development And Packaging Of A High-Density, Three-Phase, Silicon Carbide (Sic) Motor Drive, Jared Hornberger Dec 2012

The Development And Packaging Of A High-Density, Three-Phase, Silicon Carbide (Sic) Motor Drive, Jared Hornberger

Graduate Theses and Dissertations

Technology advances within the power electronics field are resulting in systems characterized by higher operating efficiencies, reduced footprint, minimal form factor, and decreasing mass. In particular, these attributes and characteristics are being inserted into numerous consumer applications, such as light-emitting diode lighting, compact fluorescent lighting, smart phones, and tablet PCs, to industrial applications that include hybrid, electric, and plug-in electric vehicles and more electric aircraft. To achieve the increase in energy efficiency and significant reduction in size and mass of these systems, power semiconductor device manufacturers are developing silicon carbide (SiC) semiconductor technology.

In this dissertation, the author discusses the …


Delay Insensitive Ternary Logic Utilizing Cmos And Cntfet, Ravi Sankar Parameswaran Nair Aug 2012

Delay Insensitive Ternary Logic Utilizing Cmos And Cntfet, Ravi Sankar Parameswaran Nair

Graduate Theses and Dissertations

As digital circuit design continues to evolve due to progress of semiconductor processes well into the sub 100nm range, clocked architectures face limitations in a number of cases where clockless asynchronous architectures require substantially less power, generate less noise, and produce less electromagnetic interference (EMI). This dissertation develops the Delay Insensitive Ternary Logic (DITL) asynchronous design paradigm that combines the designs aspects of similar Dual-Rail asynchronous paradigms and Boolean logic to create a single wire per bit, three voltage signaling and logic scheme.

DITL is designed at the transistor level using multi-threshold CMOS and carbon nanotube (CNT) FETs to develop …


Flexible Circuits For Aerospace Applications With Special Emphasis On Rf Connectors, Abhishek Nareshraj Singh Aug 2012

Flexible Circuits For Aerospace Applications With Special Emphasis On Rf Connectors, Abhishek Nareshraj Singh

Graduate Theses and Dissertations

The current work focused on the study of flexible electronic circuits for use in aerospace applications with emphasis on RF Connectors. The electrical and mechanical performance of the flexible circuits was studied and compared to a standard coaxial cable for feasibility study in avionics space. Also, Anisotropic Conductive Films (ACF) are studied for connecting the flexible RF connectors and their performance studied for electrical and mechanical behavior with change in bonding parameters.


Comparison Of Various Pipelined And Non-Pipelined Scl 8051 Alus, Jingyi Zhao Aug 2012

Comparison Of Various Pipelined And Non-Pipelined Scl 8051 Alus, Jingyi Zhao

Graduate Theses and Dissertations

This paper describes the development of an 8-bit SCL 8051 ALU with two versions: SCL 8051 ALU with nsleep and sleep signals and SCL 8051 ALU without nsleep. Both versions have combinational logic (C/L), registers, and completion components, which all utilize slept gates. Both three-stage pipelined and non-pipelined designs were examined for both versions. The four designs were compared in terms of area, speed, leakage power, average power and energy per operation. The SCL 8051 ALU without nsleep is smaller and faster, but it has greater leakage power. It also has lower average power, and less energy consumption than …


Ultra-Low Voltage Digital Circuits And Extreme Temperature Electronics Design, Aaron J. Arthurs Aug 2012

Ultra-Low Voltage Digital Circuits And Extreme Temperature Electronics Design, Aaron J. Arthurs

Graduate Theses and Dissertations

Certain applications require digital electronics to operate under extreme conditions e.g., large swings in ambient temperature, very low supply voltage, high radiation. Such applications include sensor networks, wearable electronics, unmanned aerial vehicles, spacecraft, and energyharvesting systems. This dissertation splits into two projects that study digital electronics supplied by ultra-low voltages and build an electronic system for extreme temperatures. The first project introduces techniques that improve circuit reliability at deep subthreshold voltages as well as determine the minimum required supply voltage. These techniques address digital electronic design at several levels: the physical process, gate design, and system architecture. This dissertation analyzes …


Silicon Germanium Sram And Rom Designs For Wide Temperature Range Space Applications, Matthew Barlow May 2012

Silicon Germanium Sram And Rom Designs For Wide Temperature Range Space Applications, Matthew Barlow

Graduate Theses and Dissertations

This thesis presents a design flow from specifications and feature requirements to embeddable blocks of SRAM and ROM designs from 64 bytes to 1 kilobyte that are suitable for lunar environments. The design uses the IBM SiGe 5AM BiCMOS 0.5 micron process for a synchronous memory system capable of operating at a clock frequency of 25 MHz. Radiation mitigation techniques are discussed and implemented to harden the design against total ionizing dose (TID), single-event upset (SEU), and single-event latch-up (SEL). The memory arrays are also designed to operate over the wide temperature range of -180 °C to 125 °C. Design, …


Experimental Study Of Novel Materials And Module For Cryogenic (4k) Superconducting Multi-Chip Modules, Ranjith John May 2012

Experimental Study Of Novel Materials And Module For Cryogenic (4k) Superconducting Multi-Chip Modules, Ranjith John

Graduate Theses and Dissertations

The objectives of this proposal are to understand the science and technology of interfaces in the packaging of superconducting electronic (SCE) multichip modules (MCMs) at 4 K. The thermal management issue of the current SCE-MCMs was examined and the package assembly was optimized. A novel thermally conducting and electrically insulating nano-engineered polymer was developed for the thermal management of SCE-MCMs for 4 K cryogenic packaging. Finally, the nano-engineered polymer was integrated as underfill in a SCE-MCM and the thermal and electrical performance of SCE-MCM was demonstrated at 4 K.

Niobium based superconducting electronics (SCE) are the fastest known digital logic …


Characterization And Modeling Of 4h-Sic Low Voltage Mosfets And Power Mosfets, Mihir Mudholkar May 2012

Characterization And Modeling Of 4h-Sic Low Voltage Mosfets And Power Mosfets, Mihir Mudholkar

Graduate Theses and Dissertations

The integration of low voltage and high voltage circuits on SiC has profound applications. SiC power devices have proved their superiority in terms of high temperature operation, faster switching frequencies and larger power densities when compared with Si power devices. The control of SiC power devices however, lies in the hands of low voltage circuits built on Si. Thus, there exists a separation in the overall system between the low voltage and high voltage side, which increases system cost, weight and reduces efficiency. With the advancement in low voltage SiC processing technology, low voltage control circuits can be made on …


Ultra-Low Power And Radiation Hardened Asynchronous Circuit Design, Liang Zhou May 2012

Ultra-Low Power And Radiation Hardened Asynchronous Circuit Design, Liang Zhou

Graduate Theses and Dissertations

This dissertation proposes an ultra-low power design methodology called bit-wise MTNCL for bit-wise pipelined asynchronous circuits, which combines multi-threshold CMOS (MTCMOS) with bit-wise pipelined NULL Convention Logic (NCL) systems. It provides the leakage power advantages of an all high-Vt implementation with a reasonable speed penalty compared to the all low-Vt implementation, and has negligible area overhead. It was enhanced to handle indeterminate standby states. The original MTNCL concept was enhanced significantly by sleeping Registers and Completion Logic as well as Combinational circuits to reduce area, leakage power, and energy per operation.

This dissertation also develops an architecture that allows NCL …


Investigation Of A Floating Load Buck Dc-Dc Switching Converter, Hong Tan Dec 2011

Investigation Of A Floating Load Buck Dc-Dc Switching Converter, Hong Tan

Graduate Theses and Dissertations

A floating load buck DC-DC switching converter was analyzed, simulated, designed and prototyped. The floating load buck converter is first compared to the conventional buck converter. It was found that both the floating load buck converter and conventional buck converter exhibit similar conversion characteristics despite the differences in the placement of their output inductors. A floating load buck converter was designed to be used as a high-voltage off-line light-emitting diodes (LEDs) driver using a Texas Instruments' TPS92001 controller. Finally, the characteristics of this floating load buck converter LED driver were experimentally examined.