Open Access. Powered by Scholars. Published by Universities.®
Articles 1 - 2 of 2
Full-Text Articles in Engineering
An Architecture For Configuring An Efficient Scan Path For A Subset Of Elements, Arash Ashrafi
An Architecture For Configuring An Efficient Scan Path For A Subset Of Elements, Arash Ashrafi
LSU Master's Theses
LaTeX4Web 1.4 OUTPUT Field Programmable Gate Arrays (FPGAs) have many modern applications. A feature of FPGAs is that they can be reconfigured to suit the computation. One such form of reconfiguration, called partial reconfiguration (PR), allows part of the chip to be altered. The smallest part that can be reconfigured is called a frame. To reconfigure a frame, a fixed number of configuration bits are input (typically from outside) to the frame. Thus PR involves (a) selecting a subset C Í S of k out of n frames to configure and (b) inputting the configuration bits for these k frames. …
A Study Of Fpga Resource Utilization For Pipelined Windowed Image Computations, Aswin Vijaya Varma
A Study Of Fpga Resource Utilization For Pipelined Windowed Image Computations, Aswin Vijaya Varma
LSU Master's Theses
In image processing operations, each pixel is often treated independently and operated upon by using values of other pixels in the neighborhood. These operations are often called windowed image computations (or neighborhood operations). In this thesis, we examine the implementation of a windowed computation pipeline in an FPGA-based environment. Typically, the image is generated outside the FPGA environment (such as through a camera) and the result of the windowed computation is consumed outside the FPGA environment (for example, in a screen for display or an engine for higher level analysis). The image is typically large (over a million pixels 1000×1000 …