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Full-Text Articles in Engineering
A Design Strategy To Improve Machine Learning Resiliency Of Physically Unclonable Functions Using Modulus Process, Yuqiu Jiang
A Design Strategy To Improve Machine Learning Resiliency Of Physically Unclonable Functions Using Modulus Process, Yuqiu Jiang
Theses and Dissertations
Physically unclonable functions (PUFs) are hardware security primitives that utilize non-reproducible manufacturing variations to provide device-specific challenge-response pairs (CRPs). Such primitives are desirable for applications such as communication and intellectual property protection. PUFs have been gaining considerable interest from both the academic and industrial communities because of their simplicity and stability. However, many recent studies have exposed PUFs to machine-learning (ML) modeling attacks. To improve the resilience of a system to general ML attacks instead of a specific ML technique, a common solution is to improve the complexity of the system. Structures, such as XOR-PUFs, can significantly increase the nonlinearity …
Qasm-To-Hls: A Framework For Accelerating Quantum Circuit Emulation On High-Performance Reconfigurable Computers, Anshul Maurya
Qasm-To-Hls: A Framework For Accelerating Quantum Circuit Emulation On High-Performance Reconfigurable Computers, Anshul Maurya
Theses and Dissertations
High-performance reconfigurable computers (HPRCs) make use of Field-Programmable Gate Arrays (FPGAs) for efficient emulation of quantum algorithms. Generally, algorithm-specific architectures are implemented on the FPGAs and there is very little flexibility. Moreover, mapping a quantum algorithm onto its equivalent FPGA emulation architecture is challenging. In this work, we present an automation framework for converting quantum circuits to their equivalent FPGA emulation architectures. The framework processes quantum circuits represented in Quantum Assembly Language (QASM) and derives high-level descriptions of the hardware emulation architectures for High-Level Synthesis (HLS) on HPRCs. The framework generates the code for a heterogeneous architecture consisting of a …
Accelerating Machine Learning Inference For Satellite Component Feature Extraction Using Fpgas., Andrew Ekblad
Accelerating Machine Learning Inference For Satellite Component Feature Extraction Using Fpgas., Andrew Ekblad
Theses and Dissertations
Running computer vision algorithms requires complex devices with lots of computing power, these types of devices are not well suited for space deployment. The harsh radiation environment and limited power budgets have hindered the ability of running advanced computer vision algorithms in space. This problem makes running an on-orbit servicing detection algorithm very difficult. This work proposes using a low powered FPGA to accelerate the computer vision algorithms that enable satellite component feature extraction. This work uses AMD/Xilinx’s Zynq SoC and DPU IP to run model inference. Experiments in this work centered around improving model post processing by creating implementations …
Evaluation Of Robust Deep Learning Pipelines Targeting Low Swap Edge Deployment, David Carter Cornett
Evaluation Of Robust Deep Learning Pipelines Targeting Low Swap Edge Deployment, David Carter Cornett
Masters Theses
The deep learning technique of convolutional neural networks (CNNs) has greatly advanced the state-of-the-art for computer vision tasks such as image classification and object detection. These solutions rely on large systems leveraging wattage-hungry GPUs to provide the computational power to achieve such performance. However, the size, weight and power (SWaP) requirements of these conventional GPU-based deep learning systems are not suitable when a solution requires deployment to so called "Edge" environments such as autonomous vehicles, unmanned aerial vehicles (UAVs) and smart security cameras.
The objective of this work is to benchmark FPGA-based alternatives to conventional GPU systems that have the …
Domain Specific Computing In Tightly-Coupled Heterogeneous Systems, Anthony Michael Cabrera
Domain Specific Computing In Tightly-Coupled Heterogeneous Systems, Anthony Michael Cabrera
McKelvey School of Engineering Theses & Dissertations
Over the past several decades, researchers and programmers across many disciplines have relied on Moores law and Dennard scaling for increases in compute capability in modern processors. However, recent data suggest that the number of transistors per square inch on integrated circuits is losing pace with Moores laws projection due to the breakdown of Dennard scaling at smaller semiconductor process nodes. This has signaled the beginning of a new “golden age in computer architecture” in which the paradigm will be shifted from improving traditional processor performance for general tasks to architecting hardware that executes a class of applications in a …
Compound Effects Of Clock And Voltage Based Power Side-Channel Countermeasures, Jacqueline Lagasse
Compound Effects Of Clock And Voltage Based Power Side-Channel Countermeasures, Jacqueline Lagasse
Masters Theses
The power side-channel attack, which allows an attacker to derive secret information from power traces, continues to be a major vulnerability in many critical systems. Numerous countermeasures have been proposed since its discovery as a serious vulnerability, including both hardware and software implementations. Each countermeasure has its own drawback, with some of the highly effective countermeasures incurring large overhead in area and power. In addition, many countermeasures are quite invasive to the design process, requiring modification of the design and therefore additional validation and testing to ensure its accuracy. Less invasive countermeasures that do not require directly modifying the system …
An Fpga-Based Hardware Accelerator For The Digital Image Correlation Engine, Keaten Stokke
An Fpga-Based Hardware Accelerator For The Digital Image Correlation Engine, Keaten Stokke
Graduate Theses and Dissertations
The work presented in this thesis was aimed at the development of a hardware accelerator for the Digital Image Correlation engine (DICe) and compare two methods of data access, USB and Ethernet. The original DICe software package was created by Sandia National Laboratories and is written in C++. The software runs on any typical workstation PC and performs image correlation on available frame data produced by a camera. When DICe is introduced to a high volume of frames, the correlation time is on the order of days. The time to process and analyze data with DICe becomes a concern when …
An Overlay Architecture For Pattern Matching, Rasha Elham Karakchi
An Overlay Architecture For Pattern Matching, Rasha Elham Karakchi
Theses and Dissertations
Deterministic and Non-deterministic Finite Automata (DFA and NFA) comprise the fundamental unit of work for many emerging big data applications, motivating recent efforts to develop Domain-Specific Architectures (DSAs) to exploit fine-grain parallelism available in automata workloads.
This dissertation presents NAPOLY (Non-Deterministic Automata Processor Over- LaY), an overlay architecture and associated software that attempt to maximally exploit on-chip memory parallelism for NFA evaluation. In order to avoid an upper bound in NFA size that commonly affects prior efforts, NAPOLY is optimized for runtime reconfiguration, allowing for full reconfiguration in 10s of microseconds. NAPOLY is also parameterizable, allowing for offline generation of …
Accelerating Reverse Engineering Image Processing Using Fpga, Matthew Joshua Harris
Accelerating Reverse Engineering Image Processing Using Fpga, Matthew Joshua Harris
Browse all Theses and Dissertations
In recent decades, field programmable gate arrays (FPGAs) have evolved beyond simple, expensive computational components with minimal computing power to complex, inexpensive computational engines. Today, FPGAs can perform algorithmically complex problems with improved performance compared to sequential CPUs by taking advantage of parallelization. This concept can be readily applied to the computationally dense field of image manipulation and analysis. Processed on a standard CPU, image manipulation suffers with large image sets processed by highly sequential algorithms, but by carefully adhering to data dependencies, parallelized FPGA functions or kernels offer the possibility of significant improvement through threaded CPU functions. This thesis …
Leveraging Blockchain To Mitigate The Risk Of Counterfeit Microelectronics In Its Supply Chain, Aman Ali Pogaku
Leveraging Blockchain To Mitigate The Risk Of Counterfeit Microelectronics In Its Supply Chain, Aman Ali Pogaku
Browse all Theses and Dissertations
System on Chip (SoC) is the backbone component of the electronics industry nowadays. ASIC and FPGA-based SoCs are the two most popular methods of manufacturing SoCs. However, both ASIC and FPGA industries are plagued with risks of counterfeits due to the limitations in Security, Accountability, Complexity, and Governance of their supply chain management. As a result, the current practices of these microelectronics supply chain suffer from performance and efficiency bottlenecks. In this research, we are incorporating blockchain technology into the FPGA and ASIC microelectronic supply chain to help mitigate the risk of counterfeit microelectronics through a secure and decentralized solution …
Progressive Network Deployment, Performance, And Control With Software-Defined Networking, Daniel J. Casey
Progressive Network Deployment, Performance, And Control With Software-Defined Networking, Daniel J. Casey
Theses and Dissertations
The inflexible nature of traditional computer networks has led to tightly-integrated systems that are inherently difficult to manage and secure. New designs move low-level network control into software creating software-defined networks (SDN). Augmenting an existing network with these enhancements can be expensive and complex. This research investigates solutions to these problems. It is hypothesized that an add-on device, or "shim" could be used to make a traditional switch behave as an OpenFlow SDN switch while maintaining reasonable performance. A design prototype is found to cause approximately 1.5% reduction in throughput for one ow and less than double increase in latency, …
Analysis Of High Performance Scientific Programming Workflows, Withana Kankanamalage Umayanganie Klaassen
Analysis Of High Performance Scientific Programming Workflows, Withana Kankanamalage Umayanganie Klaassen
Open Access Theses & Dissertations
Substantial time is spent on building, optimizing and maintaining large-scale software that is run on supercomputers. However, little has been done to utilize overall resources efficiently when it comes to including expensive human resources. The community is beginning to acknowledge that optimizing the hardware performance such as speed and memory bottlenecks contributes less to the overall productivity than does the development lifecycle of high-performance scientific applications. Researchers are beginning to look at overall scientific workflows for high performance computing. Scientific programming productivity is measured by time and effort required to develop, configure, and maintain a simulation experiment and its constituent …
A Proposed Approach To Hybrid Software-Hardware Application Design For Enhanced Application Performance, Alex Shipman
A Proposed Approach To Hybrid Software-Hardware Application Design For Enhanced Application Performance, Alex Shipman
Graduate Theses and Dissertations
One important aspect of many commercial computer systems is their performance; therefore, system designers seek to improve the performance next-generation systems with respect to previous generations. This could mean improved computational performance, reduced power consumption leading to better battery life in mobile devices, smaller form factors, or improvements in many areas. In terms of increased system speed and computation performance, processor manufacturers have been able to increase the clock frequency of processors up to a point, but now it is more common to seek performance gains through increased parallelism (such as a processor having more processor cores on a single …
A Hybrid Partially Reconfigurable Overlay Supporting Just-In-Time Assembly Of Custom Accelerators On Fpgas, Zeyad Tariq Aklah
A Hybrid Partially Reconfigurable Overlay Supporting Just-In-Time Assembly Of Custom Accelerators On Fpgas, Zeyad Tariq Aklah
Graduate Theses and Dissertations
The state of the art in design and development flows for FPGAs are not sufficiently mature to allow programmers to implement their applications through traditional software development flows. The stipulation of synthesis as well as the requirement of background knowledge on the FPGAs' low-level physical hardware structure are major challenges that prevent programmers from using FPGAs. The reconfigurable computing community is seeking solutions to raise the level of design abstraction at which programmers must operate, and move the synthesis process out of the programmers' path through the use of overlays. A recent approach, Just-In-Time Assembly (JITA), was proposed that enables …
Network-On-Chip Based H.264 Video Decoder On A Field Programmable Gate Array, Ian Barge
Network-On-Chip Based H.264 Video Decoder On A Field Programmable Gate Array, Ian Barge
Master's Theses (2009 -)
This thesis develops the first fully network-on-chip (NoC) based h.264 video decoder implemented in real hardware on a field programmable gate array (FPGA). This thesis starts with an overview of the h.264 video coding standard and an introduction to the NoC communication paradigm. Following this, a series of processing elements (PEs) are developed which implement the component algorithms making up the h.264 video decoder. These PEs, described primarily in VHDL with some Verilog and C, are then mapped to an NoC which is generated using the CONNECT NoC generation tool. To demonstrate the scalability of the proposed NoC based design, …
Analysis Of 3d Cone-Beam Ct Image Reconstruction Performance On A Fpga, Devin Held
Analysis Of 3d Cone-Beam Ct Image Reconstruction Performance On A Fpga, Devin Held
Electronic Thesis and Dissertation Repository
Efficient and accurate tomographic image reconstruction has been an intensive topic of research due to the increasing everyday usage in areas such as radiology, biology, and materials science. Computed tomography (CT) scans are used to analyze internal structures through capture of x-ray images. Cone-beam CT scans project a cone-shaped x-ray to capture 2D image data from a single focal point, rotating around the object. CT scans are prone to multiple artifacts, including motion blur, streaks, and pixel irregularities, therefore must be run through image reconstruction software to reduce visual artifacts. The most common algorithm used is the Feldkamp, Davis, and …
Reconfigurable Technologies For Next Generation Internet And Cluster Computing, Deepak C. Unnikrishnan
Reconfigurable Technologies For Next Generation Internet And Cluster Computing, Deepak C. Unnikrishnan
Open Access Dissertations
Modern web applications are marked by distinct networking and computing characteristics. As applications evolve, they continue to operate over a large monolithic framework of networking and computing equipment built from general-purpose microprocessors and Application Specific Integrated Circuits (ASICs) that offers few architectural choices. This dissertation presents techniques to diversify the next-generation Internet infrastructure by integrating Field-programmable Gate Arrays (FPGAs), a class of reconfigurable integrated circuits, with general-purpose microprocessor-based techniques. Specifically, our solutions are demonstrated in the context of two applications - network virtualization and distributed cluster computing.
Network virtualization enables the physical network infrastructure to be shared among several …
Hardware-Software Co-Design, Acceleration And Prototyping Of Control Algorithms On Reconfigurable Platforms, Desta Kumsa Edosa
Hardware-Software Co-Design, Acceleration And Prototyping Of Control Algorithms On Reconfigurable Platforms, Desta Kumsa Edosa
UNLV Theses, Dissertations, Professional Papers, and Capstones
Differential equations play a significant role in many disciplines of science and engineering. Solving and implementing Ordinary Differential Equations (ODEs) and partial Differential Equations (PDEs) effectively are very essential as most complex dynamic systems are modeled based on these equations. High Performance Computing (HPC) methodologies are required to compute and implement complex and data intensive applications modeled by differential equations at higher speed. There are, however, some challenges and limitations in implementing dynamic system, modeled by non-linear ordinary differential equations, on digital hardware. Modeling an integrator involves data approximation which results in accuracy error if data values are not considered …
Extending The Hybridthread Smp Model For Distributed Memory Systems, Eugene Anthony Cartwright Iii
Extending The Hybridthread Smp Model For Distributed Memory Systems, Eugene Anthony Cartwright Iii
Graduate Theses and Dissertations
Memory Hierarchy is of growing importance in system design today. As Moore's Law allows system designers to include more processors within their designs, data locality becomes a priority. Traditional multiprocessor systems on chip (MPSoC) experience difficulty scaling as the quantity of processors increases. This challenge is common behavior of memory accesses in a shared memory environment and causes a decrease in memory bandwidth as processor numbers increase. In order to provide the necessary levels of scalability, the computer architecture community has sought to decentralize memory accesses by distributing memory throughout the system. Distributed memory offers greater bandwidth due to decoupled …
A Field Programmable Gate Array Architecture For Two-Dimensional Partial Reconfiguration, Fei Wang
A Field Programmable Gate Array Architecture For Two-Dimensional Partial Reconfiguration, Fei Wang
Browse all Theses and Dissertations
Reconfigurable machines can accelerate many applications by adapting to their needs through hardware reconfiguration. Partial reconfiguration allows the reconfiguration of a portion of a chip while the rest of the chip is busy working on tasks. Operating system models have been proposed for partially reconfigurable machines to handle the scheduling and placement of tasks. They are called OS4RC in this dissertation. The main goal of this research is to address some problems that come from the gap between OS4RC and existing chip architectures and the gap between OS4RC models and practical applications. Some existing OS4RC models are based on an …