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Optimizing Dynamic Logic Realizations For Partial Reconfiguration Of Field Programmable Gate Arrays, Matthew Parris
Optimizing Dynamic Logic Realizations For Partial Reconfiguration Of Field Programmable Gate Arrays, Matthew Parris
Electronic Theses and Dissertations
Many digital logic applications can take advantage of the reconfiguration capability of Field Programmable Gate Arrays (FPGAs) to dynamically patch design flaws, recover from faults, or time-multiplex between functions. Partial reconfiguration is the process by which a user modifies one or more modules residing on the FPGA device independently of the others. Partial Reconfiguration reduces the granularity of reconfiguration to be a set of columns or rectangular region of the device. Decreasing the granularity of reconfiguration results in reduced configuration filesizes and, thus, reduced configuration times. When compared to one bitstream of a non-partial reconfiguration implementation, smaller modules resulting in …
Metadata And Data Management In High Performance File And Storage Systems, Peng Gu
Metadata And Data Management In High Performance File And Storage Systems, Peng Gu
Electronic Theses and Dissertations
With the advent of emerging "e-Science" applications, today's scientific research increasingly relies on petascale-and-beyond computing over large data sets of the same magnitude. While the computational power of supercomputers has recently entered the era of petascale, the performance of their storage system is far lagged behind by many orders of magnitude. This places an imperative demand on revolutionizing their underlying I/O systems, on which the management of both metadata and data is deemed to have significant performance implications. Prefetching/caching and data locality awareness optimizations, as conventional and effective management techniques for metadata and data I/O performance enhancement, still play their …