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Articles 31 - 40 of 40
Full-Text Articles in Engineering
Understanding Design Requirements For Building Reliable, Space-Based Fpga Mgt Systems Based On Radiation Test Results, Kevin M. Ellsworth
Understanding Design Requirements For Building Reliable, Space-Based Fpga Mgt Systems Based On Radiation Test Results, Kevin M. Ellsworth
Theses and Dissertations
Space-based computing applications often demand reliable, high-bandwidth communication systems. FPGAs with Mulit-Gigabit Transceivers (MGTs) provide an effective platform for such systems, but it is important that system designers understand the possible susceptibilities MGTs present to the system. Previous work has provided a foundation for understanding the susceptibility of raw FPGA MGTs but has fallen short of testing MGTs as part of a larger system. This work focuses on answering the questions MGT system designers need to know in order to build a reliable space-based MGT system. Two radiation tests were performed with a test architecture built on the Aurora protocol. …
Hardware And Software Fault-Tolerance Of Softcore Processors Implemented In Sram-Based Fpgas, Nathaniel Hatley Rollins
Hardware And Software Fault-Tolerance Of Softcore Processors Implemented In Sram-Based Fpgas, Nathaniel Hatley Rollins
Theses and Dissertations
Softcore processors are an attractive alternative to using expensive radiation-hardened processors for space-based applications. Since they can be implemented in the latest SRAM-based FPGA technologies, they are fast, flexible and significantly less expensive. However, unlike ASIC-based processors, the logic and routing of a softcore processor are vulnerable to the effects of single-event upsets (SEUs). To protect softcore processors from SEUs, this dissertation explores the processor design-space for the LEON3 softcore processor implemented in a commercial SRAM-based FPGA. The traditional mitigation techniques of triple modular redundancy (TMR) and duplication with compare (DWC) and checkpointing provide reliability to a softcore processor at …
Analysis And Mitigation Of Seu-Induced Noise In Fpga-Based Dsp Systems, Brian Hogan Pratt
Analysis And Mitigation Of Seu-Induced Noise In Fpga-Based Dsp Systems, Brian Hogan Pratt
Theses and Dissertations
This dissertation studies the effects of radiation-induced single-event upsets (SEUs) on digital signal processing (DSP) systems designed for field-programmable gate arrays (FPGAs). It presents a novel method for evaluating the effects of radiation on DSP and digital communication systems. By using an application-specific measurement of performance in the presence of SEUs, this dissertation demonstrates that only 5-15% of SEUs affecting a communications receiver (i.e. 5-15% of sensitive SEUs) cause critical performance loss. It also reports that the most critical SEUs are those that affect the clock, global reset, and most significant bits (MSBs) of computation. This dissertation also demonstrates …
On-Orbit Fpga Seu Mitigation And Measurement Experiments On The Cibola Flight Experiment Satellite, William A. Howes
On-Orbit Fpga Seu Mitigation And Measurement Experiments On The Cibola Flight Experiment Satellite, William A. Howes
Theses and Dissertations
This work presents on-orbit experiments conducted to validate SEU mitigation and detection techniques on FPGA devices and to measure SEU rates in FPGAs and SDRAM. These experiments were designed for the Cibola Flight Experiment Satellite (CFESat), which is an operational technology pathfinder satellite built around 9 Xilinx Virtex FPGAs and developed at Los Alamos National Laboratory. The on-orbit validation experiments described in this work have operated for over four thousand FPGA device days and have validated a variety of SEU mitigation and detection techniques including triple modular redundancy, duplication with compare, reduced precision redundancy, and SDRAM and FPGA block memory …
Synchronization Voter Insertion Algorithms For Fpga Designs Using Triple Modular Redundancy, Jonathan Mark Johnson
Synchronization Voter Insertion Algorithms For Fpga Designs Using Triple Modular Redundancy, Jonathan Mark Johnson
Theses and Dissertations
Triple Modular Redundancy (TMR) is a common reliability technique for mitigating single event upsets (SEUs) in FPGA designs operating in radiation environments. For FPGA systems that employ configuration scrubbing, majority voters are needed in all feedback paths to ensure proper synchronization between the TMR replicates. Synchronization voters, however, consume additional resources and impact system timing. This work introduces and contrasts seven algorithms for inserting synchronization voters while automatically performing TMR. The area cost and timing impact of each algorithm on a number of circuit benchmarks is reported. The work demonstrates that one of the algorithms provides the best overall timing …
Low Dislocation Density Gallium Nitride Templates And Their Device Applications, Jinqiao Xie
Low Dislocation Density Gallium Nitride Templates And Their Device Applications, Jinqiao Xie
Theses and Dissertations
The unique properties, such as large direct bandgap, excellent thermal stability, high μH × ns, of III-nitrides make them ideal candidates for both optoelectronic and high-speed electronic devices. In the past decades, great success has been achieved in commercialization of GaN based light emitting diodes (LEDs) and laser diodes (LDs). However, due to the lack of native substrates, thin films grown on sapphire or SiC substrates have high defect densities that degrade the device performance and reliability. Conventional epitaxy lateral overgrowth (ELO) can reduce dislocation densities down to ∼10-6 cm-2 in the lateral growth area, but requires ex situ photolithography …
Using Duplication With Compare For On-Line Error Detection In Fpga-Based Designs, Daniel L. Mcmurtrey
Using Duplication With Compare For On-Line Error Detection In Fpga-Based Designs, Daniel L. Mcmurtrey
Theses and Dissertations
Space destined FPGA-based systems must employ redundancy techniques to account for the effects of upsets caused by radiated environments. Error detection techniques can be used to alert external systems to the presence of these upsets. Readback with compare is an error detection technique commonly employed in FPGA-based designs. This work introduces duplication with compare (DWC) as an automated on-line error detection technique that can be used as an alternative to readback with compare. This work also introduces a set of metrics that is used to quantify the effectiveness and coverage of this error detection technique. A tool is presented that …
Estimating The Dynamic Sensitive Cross Section Of An Fpga Design Through Fault Injection, Darrel E. Johnson
Estimating The Dynamic Sensitive Cross Section Of An Fpga Design Through Fault Injection, Darrel E. Johnson
Theses and Dissertations
A fault injection tool has been created to emulate single event upset (SEU) behavior within the configuration memory of an FPGA. This tool is able to rapidly and accurately determine the dynamic sensitive cross section of the configuration memory for a given FPGA design. This tool enables the reliability of FPGA designs and fault tolerance schemes to be quickly and accurately tested. The validity of testing performed with this fault injection tool has been confirmed through radiation testing. A radiation test was conducted at Crocker Nuclear Laboratory using a proton accelerator in order to determine the actual dynamic sensitive cross …
Using Bayesian Statistics In Operational Testing, Thuan H. Tran
Using Bayesian Statistics In Operational Testing, Thuan H. Tran
Theses and Dissertations
This research explored the applicability of Bayesian methods to the problem of determining the reliability of a series system, a parallel system, and a bridge system. The time to failure of each component in each system is assumed to be exponentially distributed. A basic exponential case and a basic binomial case are also evaluated. In general, using simulated data and real data when possible, the Bayesian methods produced confidence intervals that were much tighter than the classical inference methods, thus allowing a decision maker to have higher confidence in making a decision. System level data and aggregated component level data …
Estimation Of The Captive-Carry Survival Function For The Advanced Medium Range Air-To-Air Missile (Amraam), David R. Denhard
Estimation Of The Captive-Carry Survival Function For The Advanced Medium Range Air-To-Air Missile (Amraam), David R. Denhard
Theses and Dissertations
This thesis considers the problem of estimating the survival function of an item (probability that the item functions for a time greater than a given time t) from sampling data subject to partial right censoring (a portion of the items in the sampling data have not yet been observed to fail). Specifically the thesis describes several parametric and non-parametric statistical models that can be used when the sampling data is subject to partial right censoring. These models are applied to the case of estimating the captive-carry survival function of the AIM-120A Advanced Medium Range Air-to-Air Missile (AMRAAM).