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Low-Voltage Analog Cmos Architectures And Design Methods, Kent Downing Layton
Low-Voltage Analog Cmos Architectures And Design Methods, Kent Downing Layton
Theses and Dissertations
This dissertation develops design methods and architectures which allow analog circuits to operate at VT + 2Vds,sat, the minimum supply for CMOS circuits with all transistors in the active region where Vds,sat is the drain to source saturation voltage of a MOS transistor. Techniques which meet this criteria for rail-to-rail input stages, gain enhancement stages, and output stages are discussed and developed. These techniques are used to design four fully-differential rail-to-rail amplifiers. The highest gain is shown to be attained using a drain voltage equalization (DVE) or active-bootstrapping technique which produces more than 100dB of gain in a two stage …
Dynamic Element Matching Techniques For Delta-Sigma Adcs With Large Internal Quantizers, Brent C. Nordick
Dynamic Element Matching Techniques For Delta-Sigma Adcs With Large Internal Quantizers, Brent C. Nordick
Theses and Dissertations
This thesis presents two methods that enable high internal quantizer resolution in delta-sigma analog-to-digital converters. Increasing the quantizer resolution in a delta-sigma modulator can increase SNR, improve stability and reduce integrator power consumption. However, each added bit of quantizer resolution also causes an exponential increase in the power dissipation, required area and complexity of the dynamic element matching (DEM) circuit required to attenuate digital-to-analog converter (DAC) mismatch errors. One way to overcome these drawbacks is to segment the feedback signal, creating a "coarse" signal and a "fine" signal. This reduces the DEM circuit complexity, power dissipation, and size. However, it …