Engineering Commons^™

Instrumented Control Column For Optionally Piloted Aircraft, Andrew J. Klein

Electrical Engineering

Natilus, an aerospace company that is rapid-prototyping optionally piloted aircraft (OPA) for the shipping industry, needs a system that retrieves control column position data in order to manipulate flight simulator parameters in software. At present, a universally compatible system for all aircraft does not exist. Typically, established aerospace companies will sink significant time and money into developing proprietary systems for control column data retrieval as every aircraft is unique in its layout and linkage design. However, as a startup developing their first aircraft, Natilus does not have the privilege of modifying an existing sensor system to work with their HIL …

Design Of A Sigma-Delta Adc In 65nm Cmos Process, Michael Lee Thompson Iii

Electrical Engineering Undergraduate Honors Theses

Analog and digital signals both play a vital role in electrical engineering and the technology of today. As the role of electrical and computer engineers becomes more deeply involved in the development of new technology, an understanding of how these signals are utilized, and what they represent, is a necessity. Due to the inherent limitations involved with analog signals, there is a need for these signals to be accurately and efficiently converted to digital signals for processing. The job of the analog-to-digital converter, or ADC, is to receive this analog input signal (voltage or current) and create a digital representation …

Modeling, Simulation, And Hardware Testing Of A Noise-Canceller Adc Architecture, Ethan R. Rando

Browse all Theses and Dissertations

Analog-to-Digital Converters (ADCs) are essential elements of most complex electronic devices. ADCs allow for an analog signal to be converted into the digital domain, and thus interpreted by a digital circuit or model. While ADCs are extremely common, they are not immune from common tradeoffs when being designed and implemented. The most prominent tradeoff when selecting or designing an ADC is whether to pursue a high conversion rate or a high resolution on the digital output. There are some ADC designs that allow for relatively high resolution while maintaining a respectable conversion rate, however these designs often come at the …

An 8-Bit Analog-To-Digital Converter For Battery Operated Wireless Sensor Nodes, Marvin Wayne Suggs Jr.

Graduate Theses and Dissertations

Wireless sensing networks (WSNs) collect analog information transduced into the form of a voltage or current. This data is typically converted into a digital representation of the value and transmitted wirelessly using various modulation techniques. As the available power and size is limited for wireless sensor nodes in many applications, a medium resolution Analog-to-Digital Converter (ADC) is proposed to convert a sensed voltage with moderate speeds to lower power consumption. Specifications also include a rail-to-rail input range and minimized errors associated with offset, gain, differential nonlinearity, and integral nonlinearity. To achieve these specifications, an 8-bit successive approximation register ADC is …

5-Bit Dual-Slope Analog-To-Digital Converter-Based Time-To-Digital Converter Chip Design In Cmos Technology, Jojoe S. Sagoe

LSU Master's Theses

Time-to-Digital Converters (TDC) have gained increasing importance in modern implementations of mixed-signal, data-acquisition and processing interfaces and are used to perform high precision time intervals in systems that incorporate Time-of-Flight (ToF) or Time-of-Arrival (ToA) measurements. The linearity of TDCs is very crucial since most Digital Signal Processing (DSP) systems require very linear inputs to achieve high accuracy.

In this work, a TDC has been designed in the 0.5 μm n-well CMOS process that can be used for on-chip integration and in applications requiring high linearity. This TDC used a Dual-Slope-ADC-based architecture for the time-to-digital conversion and consists of the following …

Design And Analysis Of First And Second Order K-Delta-1-Sigma Modulators In Multiple Fabrication Processes, Shada Sharif

UNLV Theses, Dissertations, Professional Papers, and Capstones

Analog to digital converters (ADC) are an important category of electronic circuits that are required in order to convert real-world analog signals into the digital domain. One of the main trade-offs in ADC design is between data conversion speed and resolution. Delta Sigma ADCs are commonly used for high precision data conversion of low bandwidth signals such as those found in audio, industrial and biomedical applications. A major disadvantage of traditional Delta Sigma ADC architectures is that they have limited signal bandwidth and are not suited for high speed applications such as communication systems. The continuous time K-Delta-1-Sigma (KD1S) modulator …

High Speed Fast Transient Digitizer Design And Simulation, Eric Clark Monahan

UNLV Theses, Dissertations, Professional Papers, and Capstones

In microelectronics, analog-to-digital converters (ADCs) are used as interfaces to convert analog inputs into discrete time or digital values that can be read via microcontrollers. As speed requirements and processing times in electronics continue to increase, high speed ADCs are increasingly critical components in the design of application-specific integrated circuits (ASICs). However, high speed ADCs introduce quantization error and are inefficient relative to size, cost, and power dissipation when compared to a High Speed Fast Transient Digitizer (HSFTD).

This thesis presents the design, layout, and simulation of a HSFTD designed to sample, in time at a fast rate, a high-speed …

Digital Enhancement Of Analog Measurement Systems For Temperature Compensation Of Strain Gages, Islombek Karimov

Electrical Engineering Theses

Generally known temperature compensation techniques for strain gages (like the use of a dummy gage or the implementation of half- and full-bridge configurations) are not applicable to all strain-measurement situations and cannot fully compensate for all sources of error. Digital Enhancement of Analog Measurement Systems presents a universal method of corrections for these effects in which temperature is measured independently of other variables and ex post facto corrections are computed and applied to digitized readings of the analog measurement system.

A single, linear-pattern strain gage, self-temperature-compensated for steel 1018, has been utilized in a quarter-bridge to measure tensile strain in …

Design And Simulation Of An 8-Bit Successive Approximation Register Charge-Redistribution Analog-To-Digital Converter, Sumit K. Verma

Electrical Engineering Theses

The thesis initially investigates the history of the monolithic ADCs. The next chapter explores the different types of ADCs available in the market today. Next, the operation of a 4-bit SAR ADC has been studied. Based on this analysis, an 8-bit charge-redistribution SAR ADC has been designed and simulated with Multisim (National Instruments, Austin, TX). The design is divided into different blocks which are individually implemented and tested. Level-1 SPICE MOSFET models representative of 5μm devices were used wherever individual MOSFETs were used in the design. Finally, the power dissipation during the conversion period was also estimated. The supply voltage …

Controlling And Processing Core For Wireless Implantable Telemetry System, Naeeme Modir

Electronic Thesis and Dissertation Repository

Wireless implantable telemetry systems are suitable choices for monitoring various physiological parameters such as blood pressure and volume. These systems typically compose of an internal device implanted into a living body captures the physiological data and sends them to an external base station located outside of the body for further processing. The internal device usually consists of a sensor interface to convert the collected data to electrical signals; a digital core to digitize the analog signals, process them and prepare them for transmission; an RF front-end to transmit the data outside the body and to receive the required commands from …

A Non-Invasive Diagnostic System For Early Assessment Of Acute Renal Transplant Rejection., Mohamed Nazih Mohamed Ibrahim Shehata

Electronic Theses and Dissertations

Early diagnosis of acute renal transplant rejection (ARTR) is of immense importance for appropriate therapeutic treatment administration. Although the current diagnostic technique is based on renal biopsy, it is not preferred due to its invasiveness, recovery time (1-2 weeks), and potential for complications, e.g., bleeding and/or infection. In this thesis, a computer-aided diagnostic (CAD) system for early detection of ARTR from 4D (3D + b-value) diffusion-weighted (DW) MRI data is developed. The CAD process starts from a 3D B-spline-based data alignment (to handle local deviations due to breathing and heart beat) and kidney tissue segmentation with an evolving geometric (level-set-based) …

Low Voltage Cmos Sar Adc Design, Ryan Hunt

Electrical Engineering

This project centers on the design of a single ended 10-bit successive approximation register analog to digital converter (SAR ADC for short) that easily interfaces to a micro-controller, such as an Arduino. With micro-controller interfacing in mind, the universal data transfer technique of SPI proved an easy way to communicate between the ADC and the micro-controller. The ADC has a range of 1V (highest code value) to 0V (lowest code value) and operates from a single voltage rail value of 1.8V. Typical SPI clock speeds run on the order of 2MHz and with a 10-bit ADC this means a sampling …

Variable Precision Tandem Analog-To-Digital Converter (Adc), Colton A. Parsons

Master's Theses

This paper describes an analog-to-digital signal converter which varies its precision as a function of input slew rate (maximum signal rate of change), in order to best follow the input in real time. It uses Flash and Successive Approximation (SAR) conversion techniques in sequence.

As part of the design, the concept of "total real-time optimization" is explored, where any delay at all is treated as an error (Error = Delay * Signal Slew Rate). This error metric is proposed for use in digital control systems. The ADC uses a 4-bit Flash converter in tandem with SAR logic that has variable …

A Jittered-Sampling Correction Technique For Adcs, Jamiil A. Tourabaly

Theses: Doctorates and Masters

In Analogue to Digital Converters (ADCs) jittered sampling raises the noise floor; this leads to a decrease in its Signal to Noise ratio (SNR) and its effective number of bits (ENOB). This research studies a technique that compensate for the effects of sampling with a jittered clock. A thorough understanding of sampling in various data converters is complied.

Low-Voltage Analog Cmos Architectures And Design Methods, Kent Downing Layton

Theses and Dissertations

This dissertation develops design methods and architectures which allow analog circuits to operate at VT + 2Vds,sat, the minimum supply for CMOS circuits with all transistors in the active region where Vds,sat is the drain to source saturation voltage of a MOS transistor. Techniques which meet this criteria for rail-to-rail input stages, gain enhancement stages, and output stages are discussed and developed. These techniques are used to design four fully-differential rail-to-rail amplifiers. The highest gain is shown to be attained using a drain voltage equalization (DVE) or active-bootstrapping technique which produces more than 100dB of gain in a two stage …

High-Speed Low-Voltage Cmos Flash Analog-To-Digital Converter For Wideband Communication System-On-A-Chip, Mingzhen Wang

Browse all Theses and Dissertations

With higher-level integration driven by increasingly complex digital systems and downscaling CMOS processes available, system-on-a-chip (SoC) is an emerging technology of low power, high cost effectiveness and high reliability and is exceedingly attractive for applications in high-speed data conversion wireless and wideband communication systems. This research presents a novel ADC comparator design methodology; the speed and performance of which is not restricted by the supply voltage reduction and device linearity deterioration in scaling-down CMOS processes. By developing a dynamic offset suppression technique and a circuit optimization method, the comparator can achieve a 3 dB frequency of 2 GHz in 130 …

On-Chip Signal Generation And Response Waveform Extraction For Analog Built-In-Self-Test, Brian Poling

Browse all Theses and Dissertations

Built-In Self-Test (BIST) is a method of designing and creating an electronic chip or an electronic system that can self test for correct functionality and ensure no manufacturing defects. The reason for analog BIST is the testing of analog parts of analog and mixed-signal ICs is a costly process that traditionally requires the use of expensive high-end automatic test equipment. Due to the nature of the testing and length of the testing process, an efficient analog BIST scheme is in high demand for the ever increasing complexity of analog and mixed-signal circuits. This thesis presents a BIST scheme for generation …

Flexible Sigma Delta Time-Interleaved Bandpass Analog-To-Digital Converter, Ryan Edward Mcginnis

Browse all Theses and Dissertations

Conversion of analog signals to their digital equivalent earlier in a circuit’s topology facilitates faster and more efficient exploitation of the information contained within. Analog-to-digital converters (ADCs) form the link between the analog and digital realms. In high frequency circuits ADCs must often be implemented further downstream after several stages of down-conversion, or through the use of more expensive technologies such as Bi-polar Junction Transistors or Gallium Arsenide. This thesis presents a technique to utilize Complimentary Metal Oxide Semiconductor technology in a parallel time-interleaved architecture. This will reduce circuit complexity and allow the ADC to be placed further upstream reducing …

Dynamic Element Matching Techniques For Delta-Sigma Adcs With Large Internal Quantizers, Brent C. Nordick

Theses and Dissertations

This thesis presents two methods that enable high internal quantizer resolution in delta-sigma analog-to-digital converters. Increasing the quantizer resolution in a delta-sigma modulator can increase SNR, improve stability and reduce integrator power consumption. However, each added bit of quantizer resolution also causes an exponential increase in the power dissipation, required area and complexity of the dynamic element matching (DEM) circuit required to attenuate digital-to-analog converter (DAC) mismatch errors. One way to overcome these drawbacks is to segment the feedback signal, creating a "coarse" signal and a "fine" signal. This reduces the DEM circuit complexity, power dissipation, and size. However, it …

First Order Sigma-Delta Modulator Of An Oversampling Adc Design In Cmos Using Floating Gate Mosfets, Syam Prasad Sbs Kommana

LSU Master's Theses

We report a new architecture for a sigma-delta oversampling analog-to-digital converter (ADC) in which the first order modulator is realized using the floating gate MOSFETs at the input stage of an integrator and the comparator. The first order modulator is designed using an 8 MHz sampling clock frequency and implemented in a standard 1.5µm n-well CMOS process. The decimator is an off-chip sinc-filter and is programmed using the VERILOG and tested with Altera Flex EPF10K70RC240 FPGA board. The ADC gives an 8-bit resolution with a 65 kHz bandwidth.