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- C-V measurements (1)
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- Chrome Masks (1)
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- Computer Programs (1)
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- E-Beam Resist (1)
- EEPROM Cell (1)
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- Electromigration (1)
- Emitter Coupled Logic (1)
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- Ferroelectric Thin Films (1)
- Four Bit CMOS ALU (1)
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Articles 1 - 30 of 37
Full-Text Articles in Engineering
Second Level Alignment Of The Pe Model 140, Louis G. Anastos
Second Level Alignment Of The Pe Model 140, Louis G. Anastos
Journal of the Microelectronic Engineering Conference
The Perkin Elmer Model 140 was investigated for second level alignment. Using a photolithographic evaluation mask, inspection of six wafers yielded overlay errors. The average x-translational error was -1.95 urn, the average y-translational error was -.4um, and the average rotational error was -.0005 uradians.
Advances In Process Modeling At Rit Suprem Iii And Minimos, John Bettencourt
Advances In Process Modeling At Rit Suprem Iii And Minimos, John Bettencourt
Journal of the Microelectronic Engineering Conference
Process technology for integrated circuit fabrication continues to change and an efficient simulation of process capability must be assured, to avoid time-consuming and costly empirical approaches. Suprem III and MINIMOS are process/device modeling programs that will permit the process/device engineer to accurately simulate complete silicon fabrication technologies. An initial report on these two software packages is given here.
Characterization Of Wells For The Cmos Process, Ed Black
Characterization Of Wells For The Cmos Process, Ed Black
Journal of the Microelectronic Engineering Conference
SUPREM simulations were run to determine a junction depth of 3um and a sheet resistance of approximately 5kohms/square to be used in wells for CMOS fabrication. From these results an experiment involving an implant energy of SO KeV, doses of 4E12/cm2, and 8E12/cm2, drive-in temperatures of 1100C and 1150C, and drive-in times between 2 and B hours was performed. Sheet resistances, measured using a four point probe, and junction depth, measured using a groove and stain tool, correlated well to SUPREM simulations.
Anaylsis Of Kti-820 Positive Resist Using The Perkin Elmer Development Rate Monitor, Maia Bodnarczuk
Anaylsis Of Kti-820 Positive Resist Using The Perkin Elmer Development Rate Monitor, Maia Bodnarczuk
Journal of the Microelectronic Engineering Conference
Experimental analysis via the Perkin Elmer Development Rate Monitor (DRM) has determined that KTI-820 resist, when exposed at 48 mJ/cm2 and developed for 30 sec in KTI-934 developer, gives optimum results. That is, 2 micron line-space pairs have been successfully reproduced with minimal sidewall sloping.
Using The Gca 4800 Dsw Wafer Stepper As A Photorepeater For The Fabrication Of Chrome And Aluminum Masks, Scott M. Bruck
Using The Gca 4800 Dsw Wafer Stepper As A Photorepeater For The Fabrication Of Chrome And Aluminum Masks, Scott M. Bruck
Journal of the Microelectronic Engineering Conference
Utilization of the GCA DSW 4800 as a PHOTOREPEATER enables the production of masks with flexibility, resolution, speed, and precision. A new chuck directly interchangeable with a standard GCA 100 Millimeter wafer chuck was machined for simple conversion from STEPPER to PHOTOREPEATER. Commercial Chrome plates and Quartz plates with thermally evaporated Aluminum films were coated with KTI-820, exposed, and etched. Chrome film resolved to 1 micron and the Etched Aluminum resolved to 3 microns.
Ecl Circuits, John J. Bush
Ecl Circuits, John J. Bush
Journal of the Microelectronic Engineering Conference
Emitter Coupled Logic (ECL) gates were fabricated on a n-epi layer. SUPREM was used to simulate the fabrication including junction depth and sheet resistance. The Integrated Circuit Editor was used to layout the design based on SUPREM parameters. SPICE was also used to confirm the proper operation of the devices. Testing was limited due to a lack of a probe card for the logic analyzer. But, an npn transistor was tested with a gain of one indicating a working device was present. A subcollector implant was not performed due to the time constrains placed on the project.
Study Of The Characteristics Of Dyed Photoresist, Brad Campbell
Study Of The Characteristics Of Dyed Photoresist, Brad Campbell
Journal of the Microelectronic Engineering Conference
Undyed, AZ 1512,and dyed, AZ 1512-SFD, photoresist was coated on aluminum covered oxide topography. The exposure was varied from 7OmJ/cm2 to 130m3/cm2 and the 3.Oum line/space pairs were measured to calculate the exposure latitude. The resist lines were examined over topography for signs of reflective notching. Results showed an increase of the exposure latitude from 9.1% to 9.9% for the dyed resist. The data was inconclusive in determining any improved control of reflective notching with the use of dyed photoresist.
Characterization Of Arc, Cynthia A. Carr
Characterization Of Arc, Cynthia A. Carr
Journal of the Microelectronic Engineering Conference
Two Anti-reflective coatings (ARC), ARC-XL end ARC-PN2, were studied f or process latitude. Temperature bake and exposure dose were varied and their effect on 5.Oum line/space pairs was evaluated. Using the software package RS1 a full factorial experiment with centerpoints was designed. The two ARCs used, did reduce notching and the manufacturer’s processing ranges were verified. However, to establish the process latitude a wider range of exposure doses needs to be evaluated.
Impurity Concentration Profile Determination By Capacitance-Voltage Measurements, David J. Cheskis
Impurity Concentration Profile Determination By Capacitance-Voltage Measurements, David J. Cheskis
Journal of the Microelectronic Engineering Conference
A FORTRAN program has been written to manipulate the data obtained from 1 MHZ C—V measurements. This program utilizes the data to compute information on the impurity profile of capacitors. Capacitors were fabricated with varying doping profiles and tested. The doping profiles obtained using this program were consistent with SUPREM models.
Computer Aided Reticle Making For A Micromotor, Stephen B. Clemens
Computer Aided Reticle Making For A Micromotor, Stephen B. Clemens
Journal of the Microelectronic Engineering Conference
The creation of MANN files, generated by computer programs, to produce other than rectangular features for the design of reticles required for the manufacturing of a micromotor has been investigated. The reticles have been designed to compensate for the lateral loss of polysilicon and silicon dioxide during the etching process and for the loss of silicon during oxidation. Three computer programs were designed to generate MANN files that would control the SCA Pattern Generator and expose emulsion coated glass plates yielding images of circles, washers, and the placement of rectangles at any orientation with respect to the center of the …
Trench Isolation Studies, John P. Curcio
Trench Isolation Studies, John P. Curcio
Journal of the Microelectronic Engineering Conference
The Tegal 700 plasma etcher was used to etch trenches into four micron deep p-type diffused resistors to evaluate the quality of the electrical isolation. Etch times of nine and twelve minutes were used to etch trenches approximately 7.B and 11.5 microns respectively. Current flow was detected in all resistors, despite the fact that the trench should have resulted in open circuits. Therefore, at this time, results are inconclusive.
Characterization Of A New E-Beam Resist, Brian Fetzer
Characterization Of A New E-Beam Resist, Brian Fetzer
Journal of the Microelectronic Engineering Conference
Waycoat HEBR-214 Positive E-beam resist was characterized for coating properties, thickness vs. dose, and thickness vs. development time. For a thickness of .5 urn, resist sensitivity was 65 uC/crn2 for a 2 minute develop, and 20 uC/cm2 for a 4 minute develop. Contrast was 6.28, which promises good resolution. Dry etch selectivity of the resist over oxide and over poly-silicon was attempted, but poor results were obtained.
Characterization Of A Silicon Nitride Plasma Etch: Selectivities And Uniformity, James H. Gardner
Characterization Of A Silicon Nitride Plasma Etch: Selectivities And Uniformity, James H. Gardner
Journal of the Microelectronic Engineering Conference
A silicon nitride plasma etch process with good nitride-to-oxide selectivity has been developed at RIT. Two fluorine etchant gases, CF4 and SF6, were characterized for etch rate and selectivities, and the effects of oxygen and hydrogen loading determined. It was found that the $~b stoh provided a selectivity of 6:1 (with a nitride etch rate of about 700 A/minute) when no loading was applied. The 3:1 CF4:02 etch demonstrated a comparable nitride etch rate, but with a poorer selectivity (about 5:2). The uniformity of the Tegal 700 plasma etching system was determined to be the limiting factor during the etch.
Determination Of Carrier Lifetime From Mos Capacitors, Kevin R. Gratzer
Determination Of Carrier Lifetime From Mos Capacitors, Kevin R. Gratzer
Journal of the Microelectronic Engineering Conference
MOS Capacitors were used to determine minority carrier lifetimes by obtaining capacitance vs time data (C-U. A test system, utilizing an IBM PC as the driver for a Princeton Applied Research model 410 C-v plotter, Kiethley programmable power supply, and HP4145 parameter analyzer, was built to obtain the C-t data. The data can then be down-loaded to the VAX mainframe computer and analyzed by various FORTRAN programs, using analytical techniques developed by people such as, Zerbst, Schroder and Guldberg, Heiman, and others.
Silyation Of Positive Photoresist, Donald R. Koszelak
Silyation Of Positive Photoresist, Donald R. Koszelak
Journal of the Microelectronic Engineering Conference
The silylation of KTI Positive Resist 809 with hexamethyldisilazane(HMDS) was performed by liquid phase and vapor phase techniques. A vacuum chamber was designed and constructed for the vapor phase silylation. Process evaluation was performed by oxygen plasma etch rates of silylated exposed and unexposed resist which showed that the vapor phase technique did change etch rates while liquid phase did not.
Electromigration Testing Of Aluminum Interconnects, David Lam
Electromigration Testing Of Aluminum Interconnects, David Lam
Journal of the Microelectronic Engineering Conference
Pure evaporated aluminum interconnects on a flat surface and over topography were subjected to high current densities of 8e5 A/cm2 and measured for Electromigration induced failure times. An electromigration test station was built and used for obtaining Mean Time to Failure, MTTF, data. A rapid statistical approach, where multiple interconnects under the identical conditions could be tested, was utilized to determine that the MTTF was lower for interconnects over topography versus flat surfaces.
Multi-Point Cleanroom Monitoring, Andrew La Pietra
Multi-Point Cleanroom Monitoring, Andrew La Pietra
Journal of the Microelectronic Engineering Conference
The feasibility of installing a multi-point particle monitoring system in the Rochester Institute of Technology Class 1000 Cleanroom at work level was examined. This consisted of monitoring 10 separate locations in the cleanroom at work level, including flow hoods, processing equipment and room air. An RS1 procedure was written to generate control charts and count information. The results showed that during low and high activity at a station the particle counts were in and out of process limits, respectively. Recommendations were made concerning installation of a complete system.
Ferroelectric Thin Films: Preparation Of A Complex Alkoxide Pbzr.5 Ti.5o3 Thin Film, Richard A. Leach
Ferroelectric Thin Films: Preparation Of A Complex Alkoxide Pbzr.5 Ti.5o3 Thin Film, Richard A. Leach
Journal of the Microelectronic Engineering Conference
Ferroelectric thin films were prepared by sd—gel processing. The complex alkoxide was prepared by reacting a Lead (II) salt with Titanium and Zirconium alkoxides in a Methoxyetharkol solvent. The gel was produced using a dilute acid catalysis to hydrolyse the bonds of the complex. The metal alkoxides were Ti/Zr isopropoxides, and Lead salt was a Lead Acetate. Working devices were not fabricated due problems in adhesion, cracking and problems with the viscosity of the gel.
Growth And Characterization Of Anodic Aluminum Oxide, Cathy Leathersich
Growth And Characterization Of Anodic Aluminum Oxide, Cathy Leathersich
Journal of the Microelectronic Engineering Conference
The growth of anodic aluminum films on silicon was investigated. The films were formed using an electrolytic cell with sulfuric acid and a lead cathode. The effects of electric potential, electrolyte concentration and anneal time were investigated with respect to film thickness, index of refraction and oxide quality with a three level-three factor Box-Behnken designed experiment. The results of the statistical analysis indicated poor repeatability in film qualities as evidenced in ellipsometric and C-V measurements.
Four Bit Cmos Alu, Frank Leilich
Four Bit Cmos Alu, Frank Leilich
Journal of the Microelectronic Engineering Conference
A four bit CMOS arithmetic logic unit was designed. The design was layed out in ICE (integrated circuit editor).
The Characterization Of An All Enhancement Pmos Op-Amp, David L. Lewis
The Characterization Of An All Enhancement Pmos Op-Amp, David L. Lewis
Journal of the Microelectronic Engineering Conference
In present day electronic systems a basic building block is the operational amplifier. Therefore, a better understanding of characteristics of Op-Amps and their importance to overall circuit operation is essential. In the electronics industry manufacturers supply data sheets for the IC’s they produce. These data sheets provide a wealth of information: absolute maximum ratings, intended applications, electrical characteristics, performance limitations, equivalent circuits of devices, and more. These defined parameters make the design of more complex systems a much easier task. As do manufacturers in the industry so too must RIT characterize their devices. This project will characterize the important parameters …
Image Reversal Optimization And A Positive Tone Lift-Off Process With Az5214-E Photoresist, Robert C. Lindstedt
Image Reversal Optimization And A Positive Tone Lift-Off Process With Az5214-E Photoresist, Robert C. Lindstedt
Journal of the Microelectronic Engineering Conference
An optimum reversal process utilizing AZ5214-E photoresist has been defined with respect to profile angle along with statistical modeling of critical variables on the resulting resist profile. A novel positive tone lift-off process was also attempted with AZ5214-E with limited success.
Greedy Channel Router Implementation In Fortran, Ray S. Linton
Greedy Channel Router Implementation In Fortran, Ray S. Linton
Journal of the Microelectronic Engineering Conference
During this project, the Greedy Channel Router was implemented in FORTRAN. This will allow students to break their general routing problems into channel routing problems to be done by the program. Since many students know FORTRAN, it will also be possible to build on the program and develop a more general router in the future [1].
Fabrication Of Air-Bridges For Millimeter Wave Integrated Circuits, Antonio L. Luciani
Fabrication Of Air-Bridges For Millimeter Wave Integrated Circuits, Antonio L. Luciani
Journal of the Microelectronic Engineering Conference
High frequencies and sub-micron geometries inherent in today’s millimeter wave integrated circuits mandate utilization of low capacitance cross-over structures such as the air-bridge. A silicon based aluminum air-bridge fabrication process is described. The structure and capacitances associated with these aluminum air-bridges was evaluated for potential use in the fabrication of integrated circuit acoustical disturbance sensors.
Construction Of A Quasi-Static C-V Test Station, Randall J. Mason
Construction Of A Quasi-Static C-V Test Station, Randall J. Mason
Journal of the Microelectronic Engineering Conference
The construction of a Quasi—Static C—V measurement tool and proper operation are presented. Gate oxides were analyzed for ion implanted regions. Guidelines for obtaining higher quality Quasi—Static C—V measurements will be presented.
Plasma Etch Optimization Of Silicon Dioxide With A Resist Mask, Eric P. Meister
Plasma Etch Optimization Of Silicon Dioxide With A Resist Mask, Eric P. Meister
Journal of the Microelectronic Engineering Conference
A dry etch process was developed and characterized to etch silicon dioxide (Si02). Characterization included increasing the etch rate o-f Si02 while decreasing the etch rate of a KTIB2O positive photoresist mask, which is used in RIT’s fabrication processes. Successful masking and etching of silicon dioxide occurred with 15 sccm CHF3 mixed with 6 sccm 02 at a chamber pressure of 750 - 800 mtorr and a power of 100 watts.
Design Of A Eeprom Cell And Thin Oxide Evaluation, Kenneth Obuszewski
Design Of A Eeprom Cell And Thin Oxide Evaluation, Kenneth Obuszewski
Journal of the Microelectronic Engineering Conference
An electrically erasable programmable read only memory (EEPROM) device, utilizing a double polysilicon structure was designed. An extremely thin gate oxide (100 ) was required to allow for Fowler-Nordheim tunneling. Thin oxide polysilicon gate capacitors were fabricated, and evidence of tunneling was existent. However, the oxide integrity was generally poor, and processing did not proceed past this point
Process Development Of Multilevel Metallization Utilizing National Semiconductor Polyimide El-5510, Ross Patterson
Process Development Of Multilevel Metallization Utilizing National Semiconductor Polyimide El-5510, Ross Patterson
Journal of the Microelectronic Engineering Conference
This project is concerned with double-layer metal using National Polyimide EL-5500 as the of an aluminum /dielectric/ aluminum scheme. The polyimide was an attractive candidate for the dielectric die to its use in trilayer resist schemes. However, results obtained showed incomplete via clear-out.
Characterization Of Integrated Injection Logic, Tu T. Phan
Characterization Of Integrated Injection Logic, Tu T. Phan
Journal of the Microelectronic Engineering Conference
Integrated Injection Logic gates (IlL) were fabricated at RIT by the use of a double diffused, four mask process. The IlL devices contained neither a buried contact nor an epitaxial layer. The propagation delay time of invertor gates was measured at different injection current levels.
Fabrication Of A Single Level Metal Ccd Shift Register, Paul F. Picano
Fabrication Of A Single Level Metal Ccd Shift Register, Paul F. Picano
Journal of the Microelectronic Engineering Conference
Using a “shadow mask” technique, a single level metal 3-phase CCD shift register was fabricated with electrode separations of 2.5 microns. Testing is pending at this time.