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Full-Text Articles in Engineering
Voltage Scaled Low Power Dnn Accelerator Design On Reconfigurable Platform, Rourab Paul, Sreetama Sarkar, Suman Sau, Sanghamitra Roy, Koushik Chakraborty, Amlan Chakrabarti
Voltage Scaled Low Power Dnn Accelerator Design On Reconfigurable Platform, Rourab Paul, Sreetama Sarkar, Suman Sau, Sanghamitra Roy, Koushik Chakraborty, Amlan Chakrabarti
Electrical and Computer Engineering Faculty Publications
The exponential emergence of Field-Programmable Gate Arrays (FPGAs) has accelerated research on hardware implementation of Deep Neural Networks (DNNs). Among all DNN processors, domain-specific architectures such as Google’s Tensor Processor Unit (TPU) have outperformed conventional GPUs (Graphics Processing Units) and CPUs (Central Processing Units). However, implementing low-power TPUs in reconfigurable hardware remains a challenge in this field. Voltage scaling, a popular approach for energy savings, can be challenging in FPGAs, as it may lead to timing failures if not implemented appropriately. This work presents an ultra-low-power FPGA implementation of a TPU for edge applications. We divide the systolic array of …
A Scalable Approach To Minimize Charging Costs For Electric Bus Fleets, Daniel Mortensen, Jacob Gunther
A Scalable Approach To Minimize Charging Costs For Electric Bus Fleets, Daniel Mortensen, Jacob Gunther
Electrical and Computer Engineering Faculty Publications
Incorporating battery electric buses into bus fleets faces three primary challenges: a BEB’s extended refuel time, the cost of charging, both by the consumer and the power provider, and large compute demands for planning methods. When BEBs charge, the additional demands on the grid may exceed hardware limitations, so power providers divide a consumer’s energy needs into separate meters even though doing so is expensive for both power providers and consumers. Prior work has developed a number of strategies for computing charge schedules for bus fleets; however, prior work has not worked to reduce costs by aggregating meters. Additionally, because …
Understanding Timing Error Characteristics From Overclocked Systolic Multiply–Accumulate Arrays In Fpgas, Andrew Chamberlin, Andrew Gerber, Mason Palmer, Tim Goodale, Noel Daniel Gundi, Koushik Chakraborty, Sanghamitra Roy
Understanding Timing Error Characteristics From Overclocked Systolic Multiply–Accumulate Arrays In Fpgas, Andrew Chamberlin, Andrew Gerber, Mason Palmer, Tim Goodale, Noel Daniel Gundi, Koushik Chakraborty, Sanghamitra Roy
Electrical and Computer Engineering Faculty Publications
Artificial Intelligence (AI) hardware accelerators have seen tremendous developments in recent years due to the rapid growth of AI in multiple fields. Many such accelerators comprise a Systolic Multiply–Accumulate Array (SMA) as its computational brain. In this paper, we investigate the faulty output characterization of an SMA in a real silicon FPGA board. Experiments were run on a single Zybo Z7-20 board to control for process variation at nominal voltage and in small batches to control for temperature. The FPGA is rated up to 800 MHz in the data sheet due to the max frequency of the PLL, but the …