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Articles 601 - 627 of 627
Full-Text Articles in Engineering
A Vhdl Design Of A Reconfigurable Cache Memory System, Tiffany M. Brooks
A Vhdl Design Of A Reconfigurable Cache Memory System, Tiffany M. Brooks
Honors Capstone Projects and Theses
No abstract provided.
The Fat-Pyramid And Universal Parallel Computation Independent Of Wire Delay, Ronald I. Greenberg
The Fat-Pyramid And Universal Parallel Computation Independent Of Wire Delay, Ronald I. Greenberg
Computer Science: Faculty Publications and Other Works
This paper shows that a fat-pyramid of area Θ(A) requires only O(log A) slowdown to simulate any competing network of area A under very general conditions. The result holds regardless of the processor size (amount of attached memory) and number of processors in the competing networks as long as the limitation on total area is met. Furthermore, the result is valid regardless of the relationship between wire length and wire delay. We especially focus on elimination of the common simplifying assumption that unit time suffices to traverse a wire regardless of its length, since the assumption becomes more and more …
Accelerating Conservative Parallel Simulation Of Vhdl Circuits, Joel F. Hurford
Accelerating Conservative Parallel Simulation Of Vhdl Circuits, Joel F. Hurford
Theses and Dissertations
This research effort considers heuristic and cost model based techniques for the optimal partitioning of VHDL circuits for parallel simulation. Correlation statistics are gathered on a wide variety of graph-based a priori parameters. Linear regression is used to identify significant parameters for inclusion in a representative cost model. Driving a greedy search, this cost model is used to improve upon initial heuristic partitions. The influence of feedback dominated previous research so a no-feedback algorithm is used to create the initial partition The circuits studied range from 1,050 to 4,243 gates.
The Evaluation Of Device Model Dependence In The Design Of A High-Frequency, Analog, Cmos Transconductance-C Filter, Susan Rose Brotman
The Evaluation Of Device Model Dependence In The Design Of A High-Frequency, Analog, Cmos Transconductance-C Filter, Susan Rose Brotman
Dissertations and Theses
It is important to have the ability to predict the effects of device model variation when designing integrated transconductance-C type active filters. Applying these filters to integrated circuit design has become increasingly popular due to its ease of implementation in monolithic form. With the introduction of fully automated design tools, predictable behavior of high-level variables becomes still more important. The purpose of this study is to evaluate the process parameter spread of analog device models to determine the effect on the design parameters of an active filter. This information's significant contribution directly effects the feasibility and realization of automating analog …
Multithreaded Computer Architecture: A Summary Of The State Of The Art, Robert Iannucci, Guang Gao, Robert Halstead, Burton Smith
Multithreaded Computer Architecture: A Summary Of The State Of The Art, Robert Iannucci, Guang Gao, Robert Halstead, Burton Smith
Robert A Iannucci
No abstract provided.
Parallel Algorithms For Single-Layer Channel Routing, Ronald I. Greenberg, Shih-Chuan Hung, Jau-Der Shih
Parallel Algorithms For Single-Layer Channel Routing, Ronald I. Greenberg, Shih-Chuan Hung, Jau-Der Shih
Computer Science: Faculty Publications and Other Works
We provide efficient parallel algorithms for the minimum separation, offset range, and optimal offset problems for single-layer channel routing. We consider all the variations of these problems that have linear-time sequential solutions rather than limiting attention to the ``river-routing'' context, where single-sided connections are disallowed. For the minimum separation problem, we obtain O(lgN) time on a CREW PRAM or O(lgN/lglgN) time on a CRCW PRAM, both with optimal work (processor-time product) of O(N), where N is the number of terminals. For the offset range problem, we obtain the same time and processor bounds as long as only one side of …
Partitioning Structural Vhdl Circuits For Parallel Execution On Hypercubes, Kevin L. Kapp
Partitioning Structural Vhdl Circuits For Parallel Execution On Hypercubes, Kevin L. Kapp
Theses and Dissertations
Distributing simulations among multiple processors is one approach to reducing VHDL simulation time for large VLSI circuit designs. However, parallel simulation introduces the problem of how to partition the logic gates and system behaviors among the available processors in order to obtain maximum speedup. This research investigates deliberate partitioning algorithms that account for the complex inter-dependency structure of the circuit behaviors. Once an initial partition has been obtained, a border annealing algorithm is used to iteratively improve the partition. In addition, methods of measuring the cost of a partition and relating it to the resulting simulation performance are investigated. Structural …
A Physics-Based Heterojunction Bipolar Transistor Model For Integrated Circuit Simulation, James A. Fellows
A Physics-Based Heterojunction Bipolar Transistor Model For Integrated Circuit Simulation, James A. Fellows
Theses and Dissertations
The purpose of this research effort was to derive a physics-based dc model for a Heterojunction Bipolar Transistor HBT. The dc model was then linearized to arrive at a small-signal model that accurately predicts the devices electrical behavior at microwave frequencies. This new model offers features not found in previous analytical or physics-based HBT models such as consideration of a cylindrical emitter-base geometry and is direct implementation into SPICE Simulation Program with Integrated Circuit Emphasis. The device model parameters were determined from a knowledge of the device material, geometry, and fabrication process. The model was then developed by using semiconductor …
Feasible Offset And Optimal Offset For Single-Layer Channel Routing, Ronald I. Greenberg, Jau-Der Shih
Feasible Offset And Optimal Offset For Single-Layer Channel Routing, Ronald I. Greenberg, Jau-Der Shih
Computer Science: Faculty Publications and Other Works
The paper provides an efficient method to find all feasible offsets for a given separation in a VLSI channel routing problem in one layer. The prior literature considers this task only for problems with no single-sided nets. When single-sided nets are included, the worst-case solution time increases from Theta(n) to Omega(n^2), where n is the number of nets. But, if the number of columns c is O(n), one can solve the problem in time O(n^{1.5}lg n ), which improves upon a `naive' O(cn) approach. As a corollary of this result, the same time bound suffices to find the optimal offset …
A Systolic Simulation And Transformation System, Ronald I. Greenberg, H.-C. Oh
A Systolic Simulation And Transformation System, Ronald I. Greenberg, H.-C. Oh
Computer Science: Faculty Publications and Other Works
This paper presents a CAD tool, SystSim, to ease the design of systolic systems. Given a high-level, functional description of processors, and a high-level description of their interconnection, SystSim will perform simulations and provide graphical output. SystSim will also perform transformations such as retiming, which eases use of the methodology of Leiserson and Saxe of designing a system with broadcasting and then obtaining a systolic system through retiming.
Minimizing Channel Density With Movable Terminals, Ronald I. Greenberg, Jau-Der Shih
Minimizing Channel Density With Movable Terminals, Ronald I. Greenberg, Jau-Der Shih
Computer Science: Faculty Publications and Other Works
We give algorithms to minimize density for channels with terminals that are movable subject to certain constraints. The main cases considered are channels with linear order constraints, channels with linear order constraints and separation constraints, channels with movable modules containing fixed terminals, and channels with movable modules and terminals. In each case, previous results for running time and space are improved by a factor of L/lg n and L , respectively, where L is the channel length and n is the number of terminals.
On The Difficulty Of Manhattan Channel Routing, Ronald I. Greenberg, Joseph Jaja, Sridhar Krishnamurthy
On The Difficulty Of Manhattan Channel Routing, Ronald I. Greenberg, Joseph Jaja, Sridhar Krishnamurthy
Computer Science: Faculty Publications and Other Works
We show that channel routing in the Manhattan model remains difficult even when all nets are single-sided. Given a set of n single-sided nets, we consider the problem of determining the minimum number of tracks required to obtain a dogleg-free routing. In addition to showing that the decision version of the problem isNP-complete, we show that there are problems requiring at least d+Omega(sqrt(n)) tracks, where d is the density. This existential lower bound does not follow from any of the known lower bounds in the literature.
Minimum Separation For Single-Layer Channel Routing, Ronald I. Greenberg, F. Miller Maley
Minimum Separation For Single-Layer Channel Routing, Ronald I. Greenberg, F. Miller Maley
Computer Science: Faculty Publications and Other Works
We present a linear-time algorithm for determining the minimum height of a single-layer routing channel. The algorithm handles single-sided connections and multiterminal nets. It yields a simple routability test for single-layer switchboxes, correcting an error in the literature.
Finding A Maximum-Density Planar Subset Of A Set Of Nets In A Channel, Ronald I. Greenberg, Jau-Der Shih
Finding A Maximum-Density Planar Subset Of A Set Of Nets In A Channel, Ronald I. Greenberg, Jau-Der Shih
Computer Science: Faculty Publications and Other Works
We present efficient algorithms to find a maximum-density planar subset of n 2-pin nets in a channel. The simplest approach is to make repeated usage of Supowit's dynamic programming algorithm for finding a maximum-size planar subset, which leads to O(n^3) time to find a maximum-density planar subset. But we also provide an algorithm whose running time is dependent on other problem parameters and is often more efficient. A simple bound on the running time of this algorithm is O(nlgn+n(t+1)w), where t is the number of two-sided nets, and w is the number of nets in the output. Though the worst-case …
High Performance Memory System Pct:Ep0199134, Robert Iannucci
High Performance Memory System Pct:Ep0199134, Robert Iannucci
Robert A Iannucci
No abstract provided.
Parallel Machines: Parallel Machine Languages, Robert Iannucci
Parallel Machines: Parallel Machine Languages, Robert Iannucci
Robert A Iannucci
No abstract provided.
Efficient Interconnection Schemes For Vlsi And Parallel Computation, Ronald I. Greenberg
Efficient Interconnection Schemes For Vlsi And Parallel Computation, Ronald I. Greenberg
Computer Science: Faculty Publications and Other Works
This thesis is primarily concerned with two problems of interconnecting components in VLSI technologies. In the first case, the goal is to construct efficient interconnection networks for general-purpose parallel computers. The second problem is a more specialized problem in the design of VLSI chips, namely multilayer channel routing. In addition, a final part of this thesis provides lower bounds on the area required for VLSI implementations of finite-state machines. This thesis shows that networks based on Leiserson's fat-tree architecture are nearly as good as any network built in a comparable amount of physical space. It shows that these "universal" networks …
Efficient Multi-Layer Channel Routing, Ronald I. Greenberg
Efficient Multi-Layer Channel Routing, Ronald I. Greenberg
Computer Science: Faculty Publications and Other Works
No abstract provided.
Versatile Potentiostat With Optional Computer Control, Gary L. Fuller, William A. Russell Jr., Roger M. Hawk, James D. Wilson, P. D. Bratton
Versatile Potentiostat With Optional Computer Control, Gary L. Fuller, William A. Russell Jr., Roger M. Hawk, James D. Wilson, P. D. Bratton
Journal of the Arkansas Academy of Science
A versatile potentiostat which can supply a maximum of 125 ma is described. The potentiostat uses readily available electronic components and an interface is detailed which allows the potentiostat optional computer control.
Randomized Routing On Fat-Trees, Ronald I. Greenberg, Charles E. Leiserson
Randomized Routing On Fat-Trees, Ronald I. Greenberg, Charles E. Leiserson
Computer Science: Faculty Publications and Other Works
Fat-trees are a class of routing networks for hardware-efficient parallel computation. This paper presents a randomized algorithm for routing messages on a fat-tree. The quality of the algorithm is measured in terms of the load factor of a set of messages to be routed, which is a lower bound on the time required to deliver the messages. We show that if a set of messages has load factor lambda on a fat-tree with n processors, the number of delivery cycles (routing attempts) that the algorithm requires is O(lambda + lg n lg lg n) with probability 1-O(1/n). The best previous …
Lower Bounds On The Area Of Finite-State Machines, M. J. Foster, Ronald I. Greenberg
Lower Bounds On The Area Of Finite-State Machines, M. J. Foster, Ronald I. Greenberg
Computer Science: Faculty Publications and Other Works
There are certain straightforward algorithms for laying out finite-state machines. This paper shows that these algorithm are optimal in the worst case for machines with fixed alphabets. That is, for any s and k, there is a deterministic finite-state machine with s states and k symbols such that any layout algorithm requires Ω(ks log s) area to lay out its realization. Similarly, any layout algorithm requires Ω(ks^2) area in the worst case for nondeterministic finite-state machines with s states and k symbols.
Mulch: A Multi-Layer Channel Router Using One, Two, And Three Layer Partitions, Ronald I. Greenberg, Alex T. Ishii, Alberto L. Sangiovanni-Vincentelli
Mulch: A Multi-Layer Channel Router Using One, Two, And Three Layer Partitions, Ronald I. Greenberg, Alex T. Ishii, Alberto L. Sangiovanni-Vincentelli
Computer Science: Faculty Publications and Other Works
Chameleon, a channel router for three layers of interconnect, has been implemented to accept specification of an arbitrary number of layers. Chameleon is based on a strategy of decomposing the multilayer problem into two- and three-layer problems in which one of the layers is reserved primarily for vertical wire runs and the other layer(s) for horizontal runs. In some situations, however, it is advantageous to consider also layers that allow the routing of entire nets, using both horizontal and vertical wires. MulCh is a multilayer channel router that extends the algorithms of Chameleon in this direction. MulCh can route channels …
Surface-To-Surface Transition Via Electromagnetic Coupling Of Coplanar Waveguides, Robert W. Jackson, David W. Matolak
Surface-To-Surface Transition Via Electromagnetic Coupling Of Coplanar Waveguides, Robert W. Jackson, David W. Matolak
Faculty Publications
A transition is investigated which couples coplanar waveguide on one substrate surface (a motherboard) to coplanar waveguide on another substrate surface (a semiconductor chip or subarray) placed above the first. No wire bonds are necessary. A full-wave analysis using coupled line theory is presented and verified experimentally. The use of this transition for coupling to millimeter-wave integrated circuits is discussed.
Method And Apparatus For Division Pct:Ep0075745, Robert Iannucci, James Kleinsteiber
Method And Apparatus For Division Pct:Ep0075745, Robert Iannucci, James Kleinsteiber
Robert A Iannucci
No abstract provided.
High Performance Memory System Utilizing Pipelining Techniques Us:4685088, Robert Iannucci
High Performance Memory System Utilizing Pipelining Techniques Us:4685088, Robert Iannucci
Robert A Iannucci
No abstract provided.
Randomized Routing On Fat-Trees, Ronald I. Greenberg
Randomized Routing On Fat-Trees, Ronald I. Greenberg
Computer Science: Faculty Publications and Other Works
Fat-trees are a class of routing networks for hardware-efficient parallel computation. This paper presents a randomized algorithm for routing messages on a fat-tree. The quality of the algorithm is measured in terms of the load factor of a set of messages to be routed, which is a lower bound on the time required to deliver the messages. We show that if a set of messages has load factor lambda on a fat-tree with n processors, the number of delivery cycles (routing attempts) that the algorithm requires is O(lambda+lgnlglgn) with probability 1-O(1/ …
Method And Apparatus For Division Employing Associative Memory Us:4466077, Robert Iannucci, James Kleinsteiber
Method And Apparatus For Division Employing Associative Memory Us:4466077, Robert Iannucci, James Kleinsteiber
Robert A Iannucci
No abstract provided.