Engineering Commons^™

Design And Implementation Of Uvm-Based Verification Framework For Deep Learning Accelerators, Randa Ahmed Hussein Aboudeif

Theses and Dissertations

Recent advancements in deep learning (DL) have made hardware accelerators, known as deep learning accelerators (DLAs), a preferred solution for numerous high-performance computing (HPC) applications, including speech recognition, computer vision, and image classification. DLAs are composed of hundreds of parallel processing engines to speed up computations and can gain access to pre-trained networks from the cloud or through on-chip memory to implement the DNN inference process. DLA verification is becoming an important and challenging phase. The verification process is required to handle the complex DLA design. Moreover, the reliability of DLAs is critical for assessment as they are involved in …

Shape Memory Alloy Capsule Micropump For Drug Delivery Applications, Youssef Mohamed Kotb

Theses and Dissertations

Implantable drug delivery devices have many benefits over traditional drug administration techniques and have attracted a lot of attention in recent years. By delivering the medication directly to the tissue, they enable the use of larger localized concentrations, enhancing the efficacy of the treatment. Passive-release drug delivery systems, one of the various ways to provide medication, are great inventions. However, they cannot dispense the medication on demand since they are nonprogrammable. Therefore, active actuators are more advantageous in delivery applications. Smart material actuators, however, have greatly increased in popularity for manufacturing wearable and implantable micropumps due to their high energy …

Physical Effects On The Worst-Case Delay Analysis And Signal Integrity Of Buses And Spirals, Mahmoud Mahany

Theses and Dissertations

Physical effects have a significant impact on the IC design which will be investigated in this thesis. Moving toward advanced technology nodes, magnetic effects become more dominant than capacitive effects. As the dimensions of the devices go down and the interconnect manipulates the circuit behavior more and more. Cross talking and voltage drops are affecting the design heavily, however - going to the full electromagnetic point of view - current return path (CRP) adds significant parasitics to the performance of the chip. Neglecting the CRP gives wrong intuition and simulation of the designs, especially that the environment and surroundings can …

Stochastic Worst-Case Test Vectors For Asic Devices In Single Event Environment, Mostafa Hemeda

Theses and Dissertations

Charged particles and energetic particles can impact the integrated circuit, referred to as single event effects (SEE). Nuclear reactors and space radiation can produce these particles. These effects can negatively affect the reliability and performance of electronics. When SEE occurs, a transient current is created, which can cause electronic devices to have incorrect outputs and ultimately fail. As a result, ensuring the reliability of ASIC circuits is a significant concern.

This thesis discusses the different fault types, then discuss the soft error and, in particular, the Single Event Transient (SET) and its causes and models. Then, this thesis proposes a …

Machine Learning Applications To Static Timing Analysis, Waseem Mohamed Raslan

Theses and Dissertations

Modeling complex cell behavior is critical for accurate static timing analysis. Effective current source model, ECSM, and composite current source, CCS, waveform data compression became a necessity to reduce the size of technology files and increase the accuracy of the cell characterization data. We used deep learning nonlinear Autoencoders to compress voltage and current waveforms and compared them with singular value decomposition, SVD, approach. Autoencoders gave ~1.67x compression ratio for voltage waveforms better than SVD approach and gave 45x to 55x better compression ratio compared to other lossless techniques like bz2 and gzip. Autoencoders achieved ~1.7x compression ratio for complex …

Integrated Circuits Parasitic Capacitance Extraction Using Machine Learning And Its Application To Layout Optimization, Mohamed Saleh Abouelyazid Saleh

Theses and Dissertations

The impact of parasitic elements on the overall circuit performance keeps increasing from one technology generation to the next. In advanced process nodes, the parasitic effects dominate the overall circuit performance. As a result, the accuracy requirements of parasitic extraction processes significantly increased, especially for parasitic capacitance extraction. Existing parasitic capacitance extraction tools face many challenges to cope with such new accuracy requirements that are set by semiconductor foundries (< 5% error). Although field-solver methods can meet such requirements, they are very slow and have a limited capacity. The other alternative is the rule-based parasitic capacitance extraction methods, which are faster and have a high capacity; however, they cannot consistently provide good accuracy as they use a pre-characterized library of capacitance formulas that cover a limited number of layout patterns. On the other hand, the new parasitic extraction accuracy requirements also added more challenges on existing parasitic-aware routing optimization methods, where simplified parasitic models are used to optimize layouts.

This dissertation provides new solutions for interconnect parasitic capacitance extraction and parasitic-aware routing optimization methodologies in order to cope with the new accuracy requirements of advanced process nodes as follows. …

Single Event Transient Sensitivity Measurement And Worst-Case Test Vector Exploration For Asic Devices Exposed To Space Single Event Environment, Mohamed Wael

Theses and Dissertations

Space radiation and nuclear reactors produce single event effects (SEE) in electronic circuits and impact their performance. The SEE phenomena cause circuits and electronic devices to fail by producing faulty results. Therefore, today’s circuit’s reliability is a significant concern for all circuit designers.

This thesis suggests a new automated flow to measure the single-event-transient (SET) effects in combinational circuits in application-specific integrated circuits (ASIC) while reaching full fault coverage. The developed flow characterizes the whole circuit nodes by identifying the most sensitive paths to the propagated SET pulses from the node under test to an observable primary output, causing single …

Network Management, Optimization And Security With Machine Learning Applications In Wireless Networks, Mariam Nabil

Theses and Dissertations

Wireless communication networks are emerging fast with a lot of challenges and ambitions. Requirements that are expected to be delivered by modern wireless networks are complex, multi-dimensional, and sometimes contradicting. In this thesis, we investigate several types of emerging wireless networks and tackle some challenges of these various networks. We focus on three main challenges. Those are Resource Optimization, Network Management, and Cyber Security. We present multiple views of these three aspects and propose solutions to probable scenarios. The first challenge (Resource Optimization) is studied in Wireless Powered Communication Networks (WPCNs). WPCNs are considered a very promising approach towards sustainable, …

On-Chip Nanoscale Plasmonic Optical Modulators, Abdalrahman Mohamed Nader Abdelhamid

Theses and Dissertations

In this thesis work, techniques for downsizing Optical modulators to nanoscale for the purpose of utilization in on chip communication and sensing applications are explored. Nanoscale optical interconnects can solve the electronics speed limiting transmission lines, in addition to decrease the electronic chips heat dissipation. A major obstacle in the path of achieving this goal is to build optical modulators, which transforms data from the electrical form to the optical form, in a size comparable to the size of the electronics components, while also having low insertion loss, high extinction ratio and bandwidth. Also, lap-on-chip applications used for fast diagnostics, …

Fault Modeling And Test Vector Generation For Asic Devices Exposed To Space Single Event Environment, Ahmed Mohamed

Theses and Dissertations

This work aims at providing a concise automated flow to predict the effect of Single Event Transients (SETs) on ASIC chips by developing a method to characterize the circuit susceptibility to SET pulses propagation and then generation of the required input vectors that sensitize the victim paths. A new enhanced method for SET electrical propagation modeling is proposed and compared to a previously published analytical model. The method was applied on different standard cells libraries built over XFAB Xh018 technology and verified for accuracy against simulations. The new method showed enhancement in accuracy compared with previous work in literature. Industrial …

Numerical Simulation Of Acoustic Wave In A Convergent-Divergent Nozzle Using A Characeristic Based Algorithm, Haitham Maher Mahmoud

Archived Theses and Dissertations

No abstract provided.