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Design And Implementation Of Benes/Clos On-Chip Interconnection Networks, Yikun Jiang
Design And Implementation Of Benes/Clos On-Chip Interconnection Networks, Yikun Jiang
UNLV Theses, Dissertations, Professional Papers, and Capstones
Networks-on-Chip (NoCs) have emerged as the key on-chip communication architecture for multiprocessor systems-on-chip and chip multiprocessors. Single-hop non-blocking networks have the advantage of providing uniform latency and throughput, which is important for cachecoherent NoC systems. Existing work shows that Benes networks have much lower transistor count and smaller circuit area but longer delay than crossbars. To reduce the delay, we propose to design the Clos network built with larger size switches. Using less than half number of stages than the Benes network, the Clos network with 4x4 switches can significantly reduce the delay. This dissertation focuses on designing high performance …