Engineering Commons^™

Testing A Quantum Computer, Marek Perkowski, Jacob D. Biamonte

Electrical and Computer Engineering Faculty Publications and Presentations

We address the problem of quantum test set generation using measurement from a single basis and the single fault model. Experimental physicists currently test quantum circuits exhaustively, meaning that each n-bit permutative circuit requires ζ x 2n tests to assure functionality, and for an m stage permutative circuit proven not to function properly the current method requires ζ x 2n x m tests as the upper bound for fault localization, where zeta varies with physical implementation. Indeed, the exhaustive methods complexity grows exponentially with the number of qubits, proportionally to the number of stages in a quantum circuit and directly …

Logic Synthesis For Layout Regularity Using Decision Diagrams, Malgorzata Chrzanowska-Jeske, Alan Mishchenko, Jinsong Zhang, Marek Perkowski

Electrical and Computer Engineering Faculty Publications and Presentations

This paper presents a methodology for logic synthesis of Boolean functions in the form of regular structures that can be mapped into standard cells or programmable devices. Regularity offers an elegant solution to hard problems arising in layout and test generation, at no extra cost or at the cost of increasing the number of gates, which does not always translate into the increase of circuit area. Previous attempts to synthesize logic into regular structures using decision diagrams suffered from an increase in the number of logic levels due to multiple repetitions of control variables. This paper proposes new techniques, which …

Fault Localization In Reversible Circuits Is Easier Than For Classical Circuits, Kavitha Ramasamy, Radhika Tagare, Edward Perkins, Marek Perkowski

Electrical and Computer Engineering Faculty Publications and Presentations

There is recently an interest in test generation for reversible circuits, but nothing has been published about fault localization in such circuits. This paper deals with fault localization for binary reversible (permutative) circuits. We concentrate on functional test based fault localization, to detect and locate “stuck-at” faults in a reversible circuit by creating an adaptive tree. A striking property of reversible circuits is that they exhibit “symmetric” adaptive trees. This helps considerably by being able to generate only half of the tree, and the other half is created as the mirror image of the first half. Because each test covers …

Deterministic And Probabilistic Test Generation For Binary And Ternary Quantum Circuits, Sowmya Aligala, Sreecharani Ratakonda, Kiran Narayan, Kanagalakshmi Nagarajan, Martin Lukac, Jacob D. Biamonte, Marek Perkowski

Electrical and Computer Engineering Faculty Publications and Presentations

It is believed that quantum computing will begin to have an impact around year 2010. Much work is done on physical realization and synthesis of quantum circuits, but nothing so far on the problem of generating tests and localization of faults for such circuits. Even fault models for quantum circuits have been not formulated yet. We propose an approach to test generation for a wide category of fault models of single and multiple faults. It uses deterministic and probabilistic tests to detect faults. A Fault Table is created that includes probabilistic information. If possible, deterministic tests are first selected, while …

Calibrating An Intracranial Pressure Dynamics Model With Clinical Data - A Progress Report, Wayne W. Wakeland, James Mcnames, Brahm Goldstein

Systems Science Faculty Publications and Presentations

We describe the calibration of a computer model of intracranial pressure (ICP) dynamics to correspond with annotated clinical data taken from a patient being treated for elevated ICP due to a traumatic brain injury. The research protocol employed during treatment includes adjusting the elevation of the head of the bed, adjusting the ventilator settings to induce mild hyperventilation and hypoventilation, and adjusting the height of the cerebrospinal fluid drainage system. The model behavior corresponds to the experimental data quite well in the case of the changing the head of the bed, but less well in the case of changing the …

A Comparison Of System Dynamics And Agent-Based Simulationapplied To The Study Of Cellular Receptor Dynamics, Wayne W. Wakeland, Edward J. Gallaher, Louis Macovsky, C. Athena Aktipis

Systems Science Faculty Publications and Presentations

Cellular receptor dynamics are often analyzed using differential equations, making system dynamics (SD) a candidate methodology. In some cases it may be useful to model the phenomena at the biomolecular level, especially when concentrations and reaction probabilities are low and might lead to unexpected behavior modes. In such cases, agent-based simulation (ABS) may be useful. We show the application of both SD and ABS to simulate non-equilibrium ligand-receptor dynamics over a broad range of concentrations, where the probability of interaction varies from low to very low. Both approaches offer much to the researcher and are complementary. We did not find …

Using Optimization To Calibrate Models Of Intracranial Pressure Dynamics To Patients With Intracranial Hypertension, Wayne W. Wakeland, A. Bulbul, Mateo Aboy, James Mcnames, Brahm Goldstein

Systems Science Faculty Publications and Presentations

Aim: Automatically calibrate ICP Dynamic model to a specific patients.

Method: Use optimization algorithm to estimate parameter values (ICP, compliances, resistances) that minimize the squared error in predicted ICP.

Results: Estimated parameter values are plausible and improve predicted ICP. Optimization time for 18 minute episode = 2.5 min. for 1 parameter, 10 to 200 min. for multiple simultaneous parameters (too long).

Logic Synthesis For Regular Fabric Realized In Quantum Dot Cellular Automata, Marek Perkowski, Alan Mishchenko

Electrical and Computer Engineering Faculty Publications and Presentations

Quantum Dot Cellular Automata are one of the most prospective nano-technologies to build digital circuits. Because of the requirements of only 2 layer wiring and noise avoidance, realizing the circuit in a regular fabrics is even more important for this technology than for classical technologies. In this paper, we propose a regular layout geometry called 3x3 lattice. The main difference of this geometry compared to the known 2x2 lattices is that it allows the cofactors on a level to propagate to three rather than two nodes on the lower level. This gives additional freedom to synthesize compact functional representations. We …

Low-Frequency Surface Wave Propagation And The Viscoelastic Behavior Of Porcine Skin, Donald D. Duncan, Sean J. Kirkpatrick, Li Fang

Electrical and Computer Engineering Faculty Publications and Presentations

A physical model describing the propagation of lowfrequency surface waves in relation to the viscoelastic behavior of porcine skin is presented, along with a series of empirical studies testing the performance of the model. The model assumes that the skin behaves as a semi-infinite, locally isotropic, viscoelastic halfspace. While the assumption of a semi-infinite body is violated, this violation does not appear to have a significant impact on the performance of the model based on the empirical studies. 1-Hz surface waves in the skin propagate primarily as Rayleigh waves with a wavelength and velocity of approximately 3 m and 3.0 …

Ultra-Thin Silicon Chips For Submillimeter-Wave Applications, Robert B. Bass, J. C. Schultz, Arthur W. Lichtenberger, R. M. Weiklel, S K. Pan, E. Bryerton, C. K. Walker, Jacob Kooi

Electrical and Computer Engineering Faculty Publications and Presentations

We present a process for fabricating ultra-thin silicon chips for submillimeter-wave mixing applications using SOI (Silicon On Insulator) wafers. Such chips allow the profile of the mixer substrate to be minimized within the microstrip channel, thereby simplifying RF design considerations and minimizing machining constraints. The chips feature gold beam leads, RF filter structures, and hot-electron bolometers as the non-linear element. We designed a prototype receiver to demonstrate the feasibility of the ultra-thin silicon chip technology. The receiver has a center frequency of 585GHz and accommodates both diffusion-cooled and phonon-cooled hotelectron bolometer mixers fabricated atop an ultra-thin silicon chip. The chip …

Exact Synthesis Of 3-Qubit Quantum Circuits From Non-Binary Quantum Gates Using Multiple-Valued Logic And Group Theory, Guowu Yang, William N. N. Hung, Xiaoyu Song, Marek Perkowski

Electrical and Computer Engineering Faculty Publications and Presentations

We propose an approach to optimally synthesize quantum circuits from non-permutative quantum gates such as Controlled-Square-Root–of-Not (i.e. Controlled-V). Our approach reduces the synthesis problem to multiple-valued optimization and uses group theory. We devise a novel technique that transforms the quantum logic synthesis problem from a multi-valued constrained optimization problem to a permutable representation. The transformation enables us to utilize group theory to exploit the symmetric properties of the synthesis problem. Assuming a cost of one for each two-qubit gate, we found all reversible circuits with quantum costs of 4, 5, 6, etc, and give another algorithm to realize these reversible …

Synthesis Of Reversible Circuits From A Subset Of Muthukrishnan-Stroud Quantum Realizable Multi-Valued Gates, Marek Perkowski, Nicholas Denler, Bruce Yen, Pawel Kerntopf

Electrical and Computer Engineering Faculty Publications and Presentations

We present a new type of quantum realizable reversible cascade. Next we present a new algorithm to synthesize arbitrary single-output ternary functions using these reversible cascades. The cascades use “Generalized Multi-Valued Gates” introduced here, which extend the concept of Generalized Ternary Gates introduced previously. While there were 216 GTGs, a total of 12 ternary gates of the new type are sufficient to realize arbitrary ternary functions. (The count can be further reduced to 5 gates, three 2-qubit and two 1-qubit). Such gates are realizable in quantum ion trap devices. For some functions, the algorithm requires fewer gates than results previously …

A Transformation Based Algorithm For Ternary Reversible Logic Synthesis Using Universally Controlled Ternary Gates, Marek Perkowski, Eric Curtis

Electrical and Computer Engineering Faculty Publications and Presentations

In this paper a synthesis algorithm for reversible ternary logic cascades is presented. The algorithm can find a solution for any reversible ternary function with n inputs and n outputs utilizing ternary inverter gates and the new (quantum realizable) UCTG gates which are a powerful generalization of ternary Toffoli gates and Generalized Ternary Gates [4]. The algorithm is an extension of the algorithm presented by Dueck, Maslov, and Miller in [3]. A unique feature of this algorithm is that it utilizes no extra wires to generate the outputs. A basic compaction algorithm is defined to improve the results of the …