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Computer-Aided Engineering and Design
University of Arkansas, Fayetteville
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Full-Text Articles in Engineering
Chip-Package Interfacial Stress Analysis And Reliability Implications For Flip-Chip Power Devices, Jonathan Gh Treco
Chip-Package Interfacial Stress Analysis And Reliability Implications For Flip-Chip Power Devices, Jonathan Gh Treco
Mechanical Engineering Undergraduate Honors Theses
The solder in flip-chip assemblies experience high stress and strain because of thermal mismatch induced deformation. These deformations occur because of the differences of coefficient of thermal expansion between flip-chip assembly materials. The similarly in stress profiles between thermal induced and shear induced stress in solder joints enable the use of die shear testing as a representative technique for relating the max stress the flip-chip can withstand to cyclic thermal fatigue failures. In this work, two electronic device sample preparation types are evaluated: One set of samples are soldered together and other set of samples use epoxy as an adhesive. …
System-Layout-Dependent Thermally Induced Solder Stress & Reliability Implications, Ange C. Iradukunda
System-Layout-Dependent Thermally Induced Solder Stress & Reliability Implications, Ange C. Iradukunda
Mechanical Engineering Undergraduate Honors Theses
Electronic flip chip assemblies consist of dissimilar component materials, which exhibit different CTE. Under thermal cyclic operating conditions, this CTE mismatch produces interfacial and interconnect stresses, which are highly dependent on system layout. In this paper, sensitivity analyses are performed using ANSYS FEA to establish how the proximity and arrangement of neighboring devices affect interconnect stress. Flip chip alignment modes ranging from edge-to-edge to corner-to-corner are studied. Results of these FEA studies, demonstrated that closely packing devices together has the effect of making them act as one. This results in a significant increase in the thermomechanical stresses induced on peripheral …