Engineering Commons^™

Profile-Guided Data Management For Heterogeneous Memory Systems, Matthew B. Olson

Doctoral Dissertations

Market forces and technological constraints have led to a gap between CPU and memory performance that has widened for decades. While processor scaling has plateaued in recent years, this gap persists and is not expected to diminish for the foreseeable future. This discrepancy presents a host of challenges for scaling application performance, which have only been exacerbated in recent years, as increasing demands for fast and effective data analytics are driving memory energy, bandwidth, and capacity requirements to new heights.

To address these trends, hardware architects have introduced a plethora of memory technologies. For example, most modern memory systems include …

Dgetmw: Motion Video Tracking Based On Memory Watershed Disc Gradient Expansion Template, Wei Wei, Kongping Wu, Laigong Guo, Qin Meng

Journal of System Simulation

Abstract: In order to obtain ideal detection results of moving object, a new video moving object detection algorithm based on labeling watershed and detection algorithm and morphology were proposed. The image was pre-processed by diffusion model to eliminate noise interference on object detection, and the difference algorithm was used to extract outline of moving object.. Morphological operations were used to process the target outline, and marked watershed algorithm was used to segment moving object and performance was tested by simulation experiments. The simulation results show that the proposed algorithm can prevent over segmentation problems and accurately detect moving object …

A Compiler Target Model For Line Associative Registers, Paul S. Eberhart

Theses and Dissertations--Electrical and Computer Engineering

LARs (Line Associative Registers) are very wide tagged registers, used for both register-wide SWAR (SIMD Within a Register )operations and scalar operations on arbitrary fields. LARs include a large data field, type tags, source addresses, and a dirty bit, which allow them to not only replace both caches and registers in the conventional memory hierarchy, but improve on both their functions. This thesis details a LAR-based architecture, and describes the design of a compiler which can generate code for a LAR-based design. In particular, type conversion, alignment, and register allocation are discussed in detail.

Solid State Drive, Shaun A. Steele

Electrical Engineering

This project documents the design and implementation of a solid state drive (SSD). SSDs are a non-volatile memory storage device that competes with hard disk drives. SSDs rely on flash memory, a type of non-volatile memory that is electrically erased and programmed. The appeal of SSDs lies in the fact that they allow a fast, reliable, and durable memory storage device. The goal of this project is to have a working external SSD built from scratch.

Exploring Spin-Transfer-Torque Devices And Memristors For Logic And Memory Applications, Zoha Pajouhi

Open Access Dissertations

As scaling CMOS devices is approaching its physical limits, researchers have begun exploring newer devices and architectures to replace CMOS.

Due to their non-volatility and high density, Spin Transfer Torque (STT) devices are among the most prominent candidates for logic and memory applications. In this research, we first considered a new logic style called All Spin Logic (ASL). Despite its advantages, ASL consumes a large amount of static power; thus, several optimizations can be performed to address this issue. We developed a systematic methodology to perform the optimizations to ensure stable operation of ASL.

Second, we investigated reliable design of …

Optimizing Main Memory Usage In Modern Computing Systems To Improve Overall System Performance, Daniel Jose Campello

FIU Electronic Theses and Dissertations

Operating Systems use fast, CPU-addressable main memory to maintain an application’s temporary data as anonymous data and to cache copies of persistent data stored in slower block-based storage devices. However, the use of this faster memory comes at a high cost. Therefore, several techniques have been implemented to use main memory more efficiently in the literature. In this dissertation we introduce three distinct approaches to improve overall system performance by optimizing main memory usage.

First, DRAM and host-side caching of file system data are used for speeding up virtual machine performance in today’s virtualized data centers. The clustering of VM …

New Challenges For The Archiving Of Digital Writing, Heiko Zimmermann

CLCWeb: Comparative Literature and Culture

In his article "New Challenges for the Archiving of Digital Writing" Heiko Zimmermann discusses the challenges of the preservation of digital texts. In addition to the problems already at the focus of attention of digital archivists, there are elements in digital literature which need to be taken into consideration when trying to archive them. Zimmermann analyses two works of digital literature, the collaborative writing project A Million Penguins (2006-2007) and Renée Tuner's She… (2008) and shows how the ontology of these texts is bound to elements of performance, to direct social interaction of writers and readers to the uniquely subjective …

Digital Circuit Projects: An Overview Of Digital Circuits Through Implementing Integrated Circuits - Second Edition, Charles W. Kann

Open Educational Resources

Digital circuits, often called Integrated Circuits or ICs, are the central building blocks of a Central Processing Unit (CPU). To understand how a computer works, it is essential to understand the digital circuits which make up the CPU. This text introduces the most important of these digital circuits; adders, decoders, multiplexers, D flip-flops, and simple state machines.

What makes this textbook unique is that it puts the ability to understand these circuits into the hands of anyone, from hobbyists to students studying Computer Science. This text is designed to teach digital circuits using simple projects the reader can implement. But …

Compacting Loads And Stores For Code Size Reduction, Isaac Asay

Master's Theses

It is important for compilers to generate executable code that is as small as possible, particularly when generating code for embedded systems. One method of reducing code size is to use instruction set architectures (ISAs) that support combining multiple operations into single operations. The ARM ISA allows for combining multiple memory operations to contiguous memory addresses into a single operation. The LLVM compiler contains a specific memory optimization to perform this combining of memory operations, called ARMLoadStoreOpt. This optimization, however, relies on another optimization (ARMPreAllocLoadStoreOpt) to move eligible memory operations into proximity in order to perform properly. This mover optimization …

Theory, Synthesis, And Application Of Adiabatic And Reversible Logic Circuits For Security Applications, Matthew Arthur Morrison

USF Tampa Graduate Theses and Dissertations

Programmable reversible logic is emerging as a prospective logic design style for implementation in modern nanotechnology and quantum computing with minimal impact on circuit heat generation. Adiabatic logic is a design methodology for reversible logic in CMOS where the current flow through the circuit is controlled such that the energy dissipation due to switching and capacitor dissipation is minimized. Recent advances in reversible logic using and quantum computer algorithms allow for improved computer architectures. Production of cost-effective Secure Integrated Chips, such as Smart Cards, requires hardware designers to consider tradeoffs in size, security, and power consumption. In order to design …